CP3SP33SMSSLASHNOPB datasheet(322/407 Pages) TI1

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Counter 1

Clock

Select

Counter 1

Clock

Counter 2

Clock

Select

Counter 2

Clock

Synchr.

External Event

Pulse Accumulator

5-Bit

Prescaler Counter

Prescaler Register

TPRSC_n

Reset

PCLK

Clock

TBn

Prescaled Clock

No Clock

DS449

Slow Clock

Synchr.

CP3SP33

SNOSCW5 – MAY 2013

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32.1.1 Timer/Counter Block

The Timer/Counter block contains the following functional blocks:

•

Two 16-bit counters, Timer/Counter 1 (TCNT1_n) and Timer/Counter 2 (TCNT2_n)

•

Two 16-bit reload/capture registers, TCRA_n and TCRB_n

•

Control logic necessary to configure the timer to operate in any of the four operating modes

•

Interrupt control and I/O control logic

32.1.2 Clock Source Block

The Clock Source block generates the signals used to clock the two timer/counter registers. The internal

structure of the Clock Source block is shown in Figure 32-2.

Figure 32-2. Multi-Function Timer Clock Source

32.1.2.1 Counter Clock Source Select

There are two clock source selectors that allow software to independently select the clock source for each

of the two 16-bit counters from any of the following sources:

•

No clock (which stops the counter)

•

Prescaled PCLK Clock

•

External event count based on TBn

•

Pulse accumulate mode based on TBn

•

Slow Clock

32.1.2.2 Prescaler

The 5-bit clock prescaler allows software to run the timer with a prescaled clock signal. The prescaler

consists of a 5- bit read/write prescaler register (TPRSC_n) and a 5-bit down counter. The PCLK Clock is

divided by the value contained in the prescaler register plus 1. Therefore, the PCLK Clock frequency can

be divided by any value from 1 to 32. The prescaler register and down counter are both cleared upon

reset.

32.1.2.3 External Event Clock

The TBn pin can be configured to operate as an external event input clock for either of the two 16-bit

counters. This input can be programmed to detect either rising or falling edges. The minimum pulse width

of the external signal is one PCLK Clock cycle. This means that the maximum frequency at which the

counter can run in this mode is one-half of the PCLK Clock frequency. This clock source is not available in

the capture modes (modes 2 and 4) because the TBn pin is used as one of the two capture inputs.

322

Dual Multi-Function Timers

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