CP3SP33SMSSLASHNOPB datasheet(325/407 Pages) TI1

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Timer/Counter 1

TCNT1_n

Timer 1

Clock

Capture A

TCRA_n

TAPND

TAn

TAIEN

Timer

Interrupt 1

Preset

Underflow

TAEN

TCPND

TCIEN

Timer

Interrupt 1

Capture B

TCRB_n

TBn

Timer/Counter 2

TnCNT2_n

Timer 2

Clock

Underflow

TDPND

TDIEN

Timer

Interrupt 2

TBPND

TBIEN

Timer

Interrupt 1

Preset

TBEN

DS452

CP3SP33

www.ti.com

SNOSCW5 – MAY 2013

32.2.2 Mode 2: Dual Input Capture

Mode 2 is the Dual Input Capture mode, which measures the elapsed time between occurrences of

external events, and which also provides a separate general-purpose timer/ counter.

Figure 32-5 is a block diagram of the Multi-Function Timer configured to operate in Mode 2. The time base

of the capture timer depends on Timer/Counter 1, which counts down using the clock selected with the

Timer/Counter 1 clock selector. The TAn and TBn pins function as capture inputs. A transition received on

the TAn pin transfers the timer contents to the TCRA_n register. Similarly, a transition received on the TBn

pin transfers the timer contents to the TCRB_n register. Each input pin can be configured to sense either

rising or falling edges.

The TAn and TBn inputs can be configured to preset the counter to FFFFh on reception of a valid capture

event. In this case, the current value of the counter is transferred to the corresponding capture register

and then the counter is preset to FFFFh. Using this approach allows software to determine the on-time

and off-time and period of an external signal with a minimum of CPU overhead.

The values captured in the TCRA_n register at different times reflect the elapsed time between transitions

on the TAn pin. The same is true for the TCRB_n register and the TBn pin. The input signal on the TAn or

TBn pin must have a pulse width equal to or greater than one PCLK Clock cycle.

There are three separate interrupts associated with the capture timer, each with its own enable bit and

pending bit. The three interrupt events are reception of a transition on the TAn pin, reception of a

transition on the TBn pin, and underflow of the TCNT1_n counter. The enable bits for these events are

TAIEN, TBIEN, and TCIEN, respectively.

In Mode 2, Timer/Counter 2 (TCNT2_n) can be used as a simple system timer. The clock counts down

using the clock selected with the Timer/Counter 2 clock selector. It asserts an interrupt upon each

underflow if the interrupt is enabled with the TDIEN bit.

Neither Timer/Counter 1 (TCNT1_n) nor Timer/Counter 2 (TCNT2_n) can be configured to operate as an

external event counter or to operate in the pulse-accumulate mode because the TBn input is used as a

capture input. Attempting to select one of these configurations will cause one or both counters to stop.

Figure 32-5. Dual-Input Capture Mode

Dual Multi-Function Timers

325

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