CP3SP33SMSSLASHNOPB datasheet(324/407 Pages) TI1

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Timer/Counter 1

TCNT1_n

Timer 1

Clock

Reload B = Time 2

TCRB_n

Reload A = Time 1

TCRA_n

TAPND

TBPND

TAIEN

Timer

Interrupt A

TAEN

TAn

TBn

TBIEN

Timer

Interrupt B

Underflow

TDIEN

Timer

Interrupt D

TDPND

Timer/Counter 2

TCNT2_n

Timer 2

Clock

Selector

DS451

CP3SP33

SNOSCW5 – MAY 2013

www.ti.com

Figure 32-4 is a block diagram of the Multi-Function Timer configured to operate in Mode 1. Timer/Counter

1 (TCNT1_n) functions as the time base for the PWM timer. It counts down at the clock rate selected for

the counter. When an underflow occurs, the timer register is reloaded alternately from the TCRA_n and

TCRB_n registers, and counting proceeds downward from the loaded value.

On the first underflow, the timer is loaded from the TCRA_n register, then from the TCRB_n register on

the next underflow, then from the TCRA_n register again on the next underflow, and so on. Every time the

counter is stopped and restarted, it always obtains its first reload value from the TCRA_n register. This is

true whether the timer is restarted upon reset, after entering Mode 1 from another mode, or after stopping

and restarting the clock with the Timer/Counter 1 clock selector.

The timer can be configured to toggle the TAn output bit on each underflow. This generates a clock signal

on the TAn output with the width and duty cycle determined by the values stored in the TCRA_n and

TCRB_n registers. This is a “processor-independent” PWM clock because once the timer is set up, no

more action is required from the CPU to generate a continuous PWM signal.

The timer can be configured to generate separate interrupts upon reload from the TCRA_n and TCRB_n

registers. The interrupts can be enabled or disabled under software control. The CPU can determine the

cause of each interrupt by looking at the TAPND and TBPND bits, which are updated by the hardware on

each occurrence of a timer reload.

In Mode 1, Timer/Counter 2 (TCNT2_n) can be used either as a simple system timer, an external event

counter, or a pulse-accumulate counter. The clock counts down using the clock selected with the

Timer/Counter 2 clock selector. It asserts an interrupt upon each underflow if the interrupt is enabled with

the TDIEN bit.

Figure 32-4. Processor-Independent PWM Mode

324

Dual Multi-Function Timers

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