DP83848JSQSLASHNOPB datasheet(62/84 Pages) TI1

62 / 84 page

DP83848H, DP83848J, DP83848K, DP83848M, DP83848T

SNLS250E – MAY 2008 – REVISED APRIL 2015

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6.6.1.2.8 10BASE-T Status/Control Register (10BTSCR)

Table 6-25. 10BASE-T Status/Control Register (10BTSCR), address 0x1A

Bit

Bit Name

Default

Description

RESERVED

0, RW

RESERVED: Must be zero.

14:12

RESERVED

0, RW

RESERVED: Must be zero.

11:9

SQUELCH

100, RW

Squelch Configuration:

Used to set the Squelch ‘ON’ threshold for the receiver.

Default Squelch ON is 330-mV peak.

LOOPBACK_10_DIS

0, RW

In half-duplex mode, default 10BASE-T operation loops Transmit data to the Receive data

in addition to transmitting the data on the physical medium. This is for consistency with

earlier 10BASE2 and 10BASE5 implementations which used a shared medium. Setting

this bit disables the loopback function.

This bit does not affect loopback due to setting BMCR[14].

LP_DIS

0, RW

Normal Link Pulse Disable:

1 = Transmission of NLPs is disabled.

0 = Transmission of NLPs is enabled.

FORCE_LINK_10

0, RW

Force 10Mb Good Link:

1 = Forced Good 10 Mb Link.

0 = Normal Link Status.

RESERVED

0, RW

RESERVED: Must be zero.

POLARITY

RO/LH

10Mb Polarity Status:

This bit is a duplication of bit 12 in the PHYSTS register. Both bits will be cleared upon a

read of 10BTSCR register, but not upon a read of the PHYSTS register.

1 = Inverted Polarity detected.

0 = Correct Polarity detected.

RESERVED

0, RW

RESERVED: Must be zero.

RESERVED

1, RW

RESERVED: Must be set to one.

HEARTBEAT_DIS

0, RW

Heartbeat Disable: This bit only has influence in half-duplex 10Mb mode.

1 = Heartbeat function disabled.

0 = Heartbeat function enabled.

When the device is operating at 100 Mb or configured for full duplex operation, this

bit will be ignored - the heartbeat function is disabled.

JABBER_DIS

0, RW

Jabber Disable:

Applicable only in 10BASE-T.

1 = Jabber function disabled.

0 = Jabber function enabled.

6.6.1.2.9 CD Test and BIST Extensions Register (CDCTRL1)

Table 6-26. CD Test and BIST Extensions Register (CDCTRL1), address 0x1B

Bit

Bit Name

Default

Description

15:8

BIST_ERROR

0, RO

BIST ERROR Counter:

_COUNT

Counts number of errored data nibbles during Packet BIST. This value will reset when

Packet BIST is restarted. The counter sticks when it reaches its max count.

7:6

RESERVED

0, RW

RESERVED: Must be zero.

BIST_CONT

0, RW

Packet BIST Continuous Mode:

_MODE

Allows continuous pseudo random data transmission without any break in transmission. This

can be used for transmit VOD testing. This is used in conjunction with the BIST controls in

the PHYCR Register (0x19h). For 10 Mb operation, jabber function must be disabled, bit 0 of

the 10BTSCR (0x1Ah), JABBER_DIS = 1.

CDPATTEN_10

0, RW

CD Pattern Enable for 10Mb:

1 = Enabled.

0 = Disabled.

RESERVED

0, RW

RESERVED: Must be zero.

Detailed Description

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Product Folder Links: DP83848H DP83848J DP83848K DP83848M DP83848T

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