DP83848JSQSLASHNOPB datasheet(31/84 Pages) TI1

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DP83848H, DP83848J, DP83848K, DP83848M, DP83848T

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SNLS250E – MAY 2008 – REVISED APRIL 2015

6.3.3.2

LED Direct Control

The DP83848x provides another option to directly control the LED outputs through the LED Direct Control

6.3.4

Internal Loopback

The DP83848x includes a Loopback Test mode for facilitating system diagnostics. The Loopback mode is

selected through bit 14 (Loopback) of the Basic Mode Control Register (BMCR). Writing 1 to this bit

enables MII transmit data to be routed to the MII receive outputs. Loopback status may be checked in bit 3

of the PHY Status Register (PHYSTS). While in Loopback mode the data will not be transmitted onto the

media. To ensure that the desired operating mode is maintained, Auto-Negotiation should be disabled

before selecting the Loopback mode.

6.3.5

BIST

The DP83848x incorporates an internal Built-in Self Test (BIST) circuit to accommodate in-circuit testing or

diagnostics. The BIST circuit can be used to test the integrity of the transmit and receive data paths. BIST

testing can be performed with the part in the internal loopback mode or externally looped back using a

loopback cable fixture.

The BIST is implemented with independent transmit and receive paths, with the transmit block generating

a continuous stream of a pseudo random sequence. The user can select a 9 bit or 15 bit pseudo random

sequence from the PSR_15 bit in the PHY Control Register (PHYCR). The received data is compared to

the generated pseudo-random data by the BIST Linear Feedback Shift Register (LFSR) to determine the

BIST pass/fail status.

The pass/fail status of the BIST is stored in the BIST status bit in the PHYCR register. The status bit

defaults to 0 (BIST fail) and will transition on a successful comparison. If an error (mis-compare) occurs,

the status bit is latched and is cleared upon a subsequent write to the Start/Stop bit.

For transmit VOD testing, the Packet BIST Continuous Mode can be used to allow continuous data

transmission, setting BIST_CONT_MODE, bit 5, of CDCTRL1 (0x1Bh).

The number of BIST errors can be monitored through the BIST Error Count in the CDCTRL1 (0x1Bh), bits

[15:8].

6.3.6

Energy Detect Mode

When Energy Detect is enabled and there is no activity on the cable, the DP83848x will remain in a low

power mode while monitoring the transmission line. Activity on the line will cause the DP83848x to go

through a normal power-up sequence. Regardless of cable activity, the DP83848x will occasionally wake

up the transmitter to put ED pulses on the line, but will otherwise draw as little power as possible. Energy

detect functionality is controlled through register Energy Detect Control (EDCR), address 0x1Dh.

6.4

Device Functional Modes

The DP83848x supports two modes of operation using the MII interface pins. The options are defined in

the following sections and include:

•

MII Mode

•

RMII Mode

The modes of operation can be selected by strap options or register control. For RMII mode, it is required

to use the strap option, because it requires a 50-MHz clock instead of the normal 25 MHz.

In the each of these modes, the IEEE 802.3 serial management interface is operational for device

configuration and status. The serial management interface of the MII allows for the configuration and

control of multiple PHY devices, gathering of status, error information, and the determination of the type

and capabilities of the attached PHY(s).

Detailed Description

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