DP83848JSQSLASHNOPB datasheet(45/84 Pages) TI1

45 / 84 page

end of packet

start of packet

VSQ-(reduced)

VSQ-

VSQ+(reduced)

VSQ+

<150 ns

>150 ns

DP83848H, DP83848J, DP83848K, DP83848M, DP83848T

www.ti.com

SNLS250E – MAY 2008 – REVISED APRIL 2015

•

Half Duplex mode

•

Full Duplex mode

Half Duplex Mode— In Half Duplex mode the DP83848x functions as a standard IEEE 802.3 10BASE-T

transceiver supporting the CSMA/CD protocol.

Full Duplex Mode — In Full Duplex mode the DP83848x is capable of simultaneously transmitting and

receiving without asserting the collision signal. The DP83848x's 10 Mb/s ENDEC is designed to encode

and decode simultaneously.

6.5.1.3.2 Smart Squelch

The smart squelch is responsible for determining when valid data is present on the differential receive

inputs. The DP83848x implements an intelligent receive squelch to ensure that impulse noise on the

receive inputs will not be mistaken for a valid signal. Smart-squelch operation is independent of the

10BASE-T operational mode.

The squelch circuitry employs a combination of amplitude and timing measurements (as specified in the

IEEE 802.3 10BSE-T standard) to determine the validity of data on the twisted-pair inputs (refer to

Figure 6-9).

The signal at the start of a packet is checked by the smart squelch and any pulses not exceeding the

squelch level (either positive or negative, depending upon polarity) will be rejected. Once this first squelch

level is overcome correctly, the opposite squelch level must then be exceeded within 150 ns. Finally, the

signal must again exceed the original squelch level within a 150 ns to ensure that the input waveform will

not be rejected. This checking procedure results in the loss of typically three preamble bits at the

beginning of each packet.

Only after all these conditions have been satisfied will a control signal be generated to indicate to the

remainder of the circuitry that valid data is present. At this time, the smart squelch circuitry is reset.

Valid data is considered to be present until the squelch level has not been generated for a time longer

than 150 ns, indicating the End of Packet. Once good data has been detected, the squelch levels are

reduced to minimize the effect of noise causing premature End of Packet detection.

Figure 6-9. 10BASE-T Twisted Pair Smart Squelch Operation

6.5.1.3.3 Collision Detection and SQE

When in Half Duplex, a 10BASE-T collision is detected when the receive and transmit channels are active

simultaneously. Collisions are reported by the COL signal on the MII. Collisions are also reported when a

jabber condition is detected.

The COL signal remains set for the duration of the collision. If the PHY is receiving when a collision is

detected it is reported immediately (through the COL pin).

Detailed Description

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Product Folder Links: DP83848H DP83848J DP83848K DP83848M DP83848T

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