DP83848JSQSLASHNOPB datasheet(44/84 Pages) TI1

44 / 84 page

DP83848H, DP83848J, DP83848K, DP83848M, DP83848T

SNLS250E – MAY 2008 – REVISED APRIL 2015

www.ti.com

Synchronization of the descrambler to the original scrambling sequence (N) is achieved based on the

knowledge that the incoming scrambled data stream consists of scrambled IDLE data. After the

descrambler has recognized 12 consecutive IDLE code-groups, where an unscrambled IDLE code-group

in 5B NRZ is equal to five consecutive ones (11111), it will synchronize to the receive data stream and

generate unscrambled data in the form of unaligned 5B code-groups.

In order to maintain synchronization, the descrambler must continuously monitor the validity of the

unscrambled data that it generates. To ensure this, a line state monitor and a hold timer are used to

constantly monitor the synchronization status. Upon synchronization of the descrambler the hold timer

starts a 722-µs countdown. Upon detection of sufficient IDLE code-groups (58 bit times) within the 722-µs

period, the hold timer will reset and begin a new countdown. This monitoring operation will continue

indefinitely given a properly operating network connection with good signal integrity. If the line state

monitor does not recognize sufficient unscrambled IDLE code-groups within the 722-µs period, the entire

descrambler will be forced out of the current state of synchronization and reset in order to re-acquire

synchronization.

6.5.1.2.10 Code-Group Alignment

The code-group alignment module operates on unaligned 5-bit data from the descrambler (or, if the

descrambler is bypassed, directly from the NRZI/NRZ decoder) and converts it into 5B code-group data (5

bits). Code-group alig ment occurs after the J/K code-group pair is detected. Once the J/K code-group pair

(11000 10001) is detected, subsequent data is aligned on a fixed boundary.

6.5.1.2.11 4B/5B Decoder

The code-group decoder functions as a look up table that translates incoming 5B code-groups into 4B

nibbles. The code-group decoder first detects the J/K code-group pair preceded by IDLE code-groups and

replaces the J/K with MAC preamble. Specifically, the J/K 10-bit code-group pair is replaced by the nibble

pair (0101 0101). All subsequent 5B code-groups are converted to the corresponding 4B nibbles for the

duration of the entire packet. This conversion ceases upon the detection of the T/R code-group pair

denoting the End of Stream Delimiter (ESD) or with the reception of a minimum of two IDLE code-groups.

6.5.1.2.12 100BASE-TX Link Integrity Monitor

The 100 Base TX Link monitor ensures that a valid and stable link is established before enabling both the

Transmit and Receive PCS layer.

Signal detect must be valid for 395 µs to allow the link monitor to enter the 'Link Up' state, and enable the

transmit and receive functions.

6.5.1.2.13 Bad SSD Detection

A Bad Start of Stream Delimiter (Bad SSD) is any transition from consecutive idle code-groups to non-idle

code-groups which is not prefixed by the code-group pair /J/K.

If this condition is detected, the DP83848x will assert RX_ER and present RXD[3:0] = 1110 to the MII for

the cycles that correspond to received 5B code-groups until at least two IDLE code groups are detected.

In addition, the False Carrier Sense Counter register (FCSCR) will be incremented by one.

Once at least two IDLE code groups are detected, RX_ER and CRS become deasserted.

6.5.1.3

10BASE-T Transceiver Module

The 10BASE-T Transceiver Module is IEEE 802.3 compliant. It includes the receiver, transmitter, collision,

heart-beat, loopback, jabber, and link integrity functions, as defined in the standard. An external filter is not

required on the 10BASE-T interface because this is integrated inside the DP83848x. This section focuses

on the general 10BASE-T system level operation.

6.5.1.3.1 Operational Modes

The DP83848x has two basic 10BASE-T operational modes:

Detailed Description

Submit Documentation Feedback

Product Folder Links: DP83848H DP83848J DP83848K DP83848M DP83848T

DP83848JSQ/NOPB bảng dữ liệu(PDF) 44 Page - Texas Instruments

DP83848JSQ/NOPB bảng dữ liệu(HTML) 44 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84

bảng dữ liệu tải về

Link URL