DP83848JSQSLASHNOPB datasheet(53/84 Pages) TI1

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DP83848H, DP83848J, DP83848K, DP83848M, DP83848T

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SNLS250E – MAY 2008 – REVISED APRIL 2015

The PHY Identifier Registers #1 and #2 together form a unique identifier for the DP83848x. The Identifier

consists of a concatenation of the Organizationally Unique Identifier (OUI), the vendor's model number

and the model revision number. A PHY may return a value of zero in each of the 32 bits of the PHY

Identifier if desired. The PHY Identifier is intended to support network management. National's IEEE

assigned OUI is 080017h.

6.6.1.1.3 PHY Identifier Register #1 (PHYIDR1)

Table 6-11. PHY Identifier Register #1 (PHYIDR1), address 0x02

Bit

Bit Name

Default

Description

15:0

OUI_MSB

<0010 0000 0000

OUI Most Significant Bits:

0000>, RO/P

Bits 3 to 18 of the OUI (080017h) are stored in bits 15 to 0 of this register. The most

significant two bits of the OUI are ignored (the IEEE standard refers to these as bits 1 and

2).

6.6.1.1.4 PHY Identifier Register #2 (PHYIDR2)

Table 6-12. PHY Identifier Register #2 (PHYIDR2), address 0x03

Bit

Bit Name

Default

Description

15:10

OUI_LSB

<0101 11>, RO/P

OUI Least Significant Bits:

Bits 19 to 24 of the OUI (080017h) are mapped from bits 15 to 10 of this register

respectively.

9:4

VNDR_MDL

<00 1001>, RO/P

Vendor Model Number:

The six bits of vendor model number are mapped from bits 9 to 4 (most significant bit to bit

9).

3:0

MDL_REV

<0000>, RO/P

Model Revision Number:

Four bits of the vendor model revision number are mapped from bits 3 to 0 (most significant

bit to bit 3). This field will be incremented for all major device changes.

6.6.1.1.5 Auto-Negotiation Advertisement Register (ANAR)

This register contains the advertised abilities of this device as they will be transmitted to its link partner

during Auto-Negotiation. Any writes to this register prior to completion of Auto-Negotiation (as indicated in

the Basic Mode Status Register (address 0x01) Auto-Negotiation complete bit, BMSR[5] ) should be

followed by a renegotiation. This will ensure that the new values are properly used in the Auto-Negotiation.

Table 6-13. Auto-Negotiation Advertisement Register (ANAR), address 0x04

Bit

Bit Name

Default

Description

0, RW

Next Page Indication:

0 = Next Page Transfer not desired.

1 = Next Page Transfer desired.

RESERVED

0, RO/P

RESERVED by IEEE: Writes ignored, Read as 0.

0, RW

Remote Fault:

1 = Advertises that this device has detected a Remote Fault.

0 = No Remote Fault detected.

RESERVED

0, RW

RESERVED for Future IEEE use: Write as 0, Read as 0

ASM_DIR

0, RW

Asymmetric PAUSE Support for Full Duplex Links:

The ASM_DIR bit indicates that asymmetric PAUSE is supported.

Encoding and resolution of PAUSE bits is defined in IEEE 802.3 Annex 28B, Tables 28B-2 and

28B-3, respectively. Pause resolution status is reported in PHYCR[13:12].

1 = Advertise that the DTE (MAC) has implemented both the optional MAC control sublayer

and the pause function as specified in clause 31 and annex 31B of 802.3.

0= No MAC based full duplex flow control.

Detailed Description

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