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The STM32L0 Cortex-M0+ Instruction Set

PM0223

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The STM32L0 Cortex-M0+ Instruction Set

3.1

Instruction set summary

The processor implements a version of the Thumb instruction set. Table 15 lists the

supported instructions.

In Table 15

•

Angle brackets, <>, enclose alternative forms of the operand.

•

Braces, {}, enclose optional operands and mnemonic parts.

•

The Operands column is not exhaustive.

For more information on the instructions and operands, see the instruction descriptions.

Table 15. STM32L0 Cortex-M0+ instructions

Mnemonic

Operands

Brief description

Flags

Section

ADCS

{Rd,} Rn, Rm

Add with Carry

N,Z,C,V

3.5.1 on page 54.

ADD{S}

{Rd,} Rn, <Rm|#imm>

Add

N,Z,C,V

3.5.1 on page 54.

ADR

Rd, label

PC-relative Address to

3.4.1 on page 46.

ANDS

{Rd,} Rn, Rm

Bitwise AND

N,Z

3.5.2 on page 56.

ASRS

{Rd,} Rm, <Rs|#imm>

Arithmetic Shift Right

N,Z,C

3.5.3 on page 57.

B{cc}

label

Branch {conditionally} -

3.6.1 on page 66.

BICS

{Rd,} Rn, Rm

Bit Clear

N,Z

3.5.2 on page 56.

BKPT

#imm

Breakpoint

3.7.1 on page 69.

label

Branch with Link

3.6.1 on page 66.

BLX

Branch indirect with

Link

3.6.1 on page 66.

Branch indirect

3.6.1 on page 66.

CMN

Rn, Rm

Compare Negative

N,Z,C,V

3.5.4 on page 59.

CMP

Rn, <Rm|#imm>

Compare

N,Z,C,V

3.5.4 on page 59.

CPSID

Change Processor

State, Disable

Interrupts

3.7.2 on page 70.

CPSIE

Change Processor

State, Enable

Interrupts

3.7.2 on page 70.

DMB

Data Memory Barrier

3.7.3 on page 71.

DSB

Data Synchronization

Barrier

3.7.4 on page 72.

EORS

{Rd,} Rn, Rm

Exclusive OR

N,Z

3.5.2 on page 56.

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