PM0223 datasheet(97/110 Pages) STMICROELECTRONICS

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PM0223

STM32L0 Core Peripherals

108

To generate a multi-shot timer with a period of N processor clock cycles, use a RELOAD

value of N-1. For example, if the SysTick interrupt is required every 100 clock pulses, set

RELOAD to 99.

4.4.3

SysTick Current Value Register (STK_CVR)

The STK_CVR contains the current value of the SysTick counter. See the register summary

in Table 33 on page 95 for its attributes. The bit assignments are:

4.4.4

SysTick Calibration Value Register (STK_CALIB)

The STK_CALIB register indicates the SysTick calibration properties. See the register

summary in Table 33 on page 95 for its attributes. The bit assignments are:

If calibration information is not known, calculate the calibration value required from the

frequency of the processor clock or external clock.

Reserved

CURRENT

rc_w

5432

CURRENT

rc_w

Bits31:24

Reserved, must be kept cleared.

Bits 23:0

CURRENT Reads return the current value of the SysTick counter.

A write of any value clears the field to 0, and also clears the SYST_CSR.COUNTFLAG bit to

REF

SKEW

Reserved

TENMS[23:16]

rrrr

5432

TENMS[15:0]

rrrr

Bit 31

NOREF: Reads as zero. Indicates that separate reference clock is provided. The frequency of

this clock is HCLK/8.

Bit 30

SKEW: Reads as one. Calibration value for the 1ms inexact timing is not known because

TENMS is not known. This can affect the suitability of SysTick as a software real time clock.

Bits 29:24

Reserved, must be kept cleared.

Bits 23:0

TENMS[23:0]:

Indicates the calibration value when the SysTick counter runs on HCLK max/8 as external

clock. The value is product dependent, please refer to the Product Reference Manual, SysTick

Calibration Value section. When HCLK is programmed at the maximum frequency, the SysTick

period is 1ms.

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