PM0223 datasheet(91/110 Pages) STMICROELECTRONICS

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PM0223

STM32L0 Core Peripherals

108

When you write to the ICSR, the effect is Unpredictable if you:

•

write 1 to the PENDSVSET bit and write 1 to the PENDSVCLR bit

•

write 1 to the PENDSTSET bit and write 1 to the PENDSTCLR bit.

4.3.4

Vector Table Offset Register

The VTOR indicates the offset of the vector table base address from memory address

0x00000000

. See the register summary for its attributes.

The bit assignments are:

4.3.5

Application Interrupt and Reset Control Register

The AIRCR provides endian status for data accesses and reset control of the system. To

write to this register, you must write 0x05FA to the VECTKEY field, otherwise the processor

ignores the write.

The bit assignments are:

[17:12] VECTPENDING r

Indicates the exception number of the highest priority pending

enabled exception:

0 = No pending exceptions.

Nonzero = the exception number of the highest priority pending

enabled exception.

Subtract 16 from this value to obtain the CMSIS IRQ number that

identifies the corresponding bit in the Interrupt Clear-Enable, Set-

Enable, Clear-Pending, Set-pending, and Priority Register, see

Table 6 on page 16.

[11:0]

Reserved.

Table 31. ICSR bit assignments (continued)

Bits

Name

Type Function

TBLOFF[31:16]

TBLOFF[15:7]

Reserved

Bits 31:7 TBLOFF Vector table base offset field.

It contains bits[31:7] of the offset of the table base from the bottom of the memory map.

Bits 6:0 Reserved

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