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PM0223 bảng dữ liệu(PDF) 56 Page - STMicroelectronics |
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PM0223 bảng dữ liệu(HTML) 56 Page - STMicroelectronics |
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56 / 110 page ![]() The STM32L0 Cortex-M0+ Instruction Set PM0223 56/110 DocID025763 Rev 1 3.5.2 AND, ORR, EOR, and BIC Logical AND, OR, Exclusive OR, and Bit Clear. Syntax ANDS {Rd,} Rn, Rm ORRS {Rd,} Rn, Rm EORS {Rd,} Rn, Rm BICS {Rd,} Rn, Rm where: Operation The AND, EOR, and ORR instructions perform bitwise AND, exclusive OR, and inclusive OR operations on the values in Rn and Rm. The BIC instruction performs an AND operation on the bits in Rn with the logical negation of the corresponding bits in the value of Rm. The condition code flags are updated on the result of the operation, see Condition flags on page 47. Restrictions In these instructions, Rd, Rn, and Rm must only specify R0-R7. Condition flags These instructions: Update the N and Z flags according to the result. Do not affect the C or V flag. Examples ANDS R2, R2, R1 ORRS R2, R2, R5 ANDS R5, R5, R8 EORS R7, R7, R6 BICS R0, R0, R1 Rd Is the destination register. Rn Is the register holding the first operand and is the same as the destination register. Rm Second register |
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