PM0223 datasheet(88/110 Pages) STMICROELECTRONICS

88 / 110 page

STM32L0 Core Peripherals

PM0223

88/110

DocID025763 Rev 1

4.3

System Control Block

The System Control Block (SCB) provides system implementation information, and system

control. This includes configuration, control, and reporting of the system exceptions. The

SCB registers are:

4.3.1

The CMSIS mapping of the STM32L0 Cortex-M0+ SCB registers

To improve software efficiency, the CMSIS simplifies the SCB register presentation. In the

CMSIS, the array SHP[1] corresponds to the registers SHPR2-SHPR3.

4.3.2

CPUID Register

The CPUID register contains the processor part number, version, and implementation

information. See the register summary in Table 30 on page 88 for its attributes. The bit

assignments are:

Table 30. Summary of the SCB registers

Address

Name

Type

Reset value

Description

0xE000ED00

CPUID RO

0x410CC601

4.3.2: CPUID Register on page 88.

0xE000ED04

ICSR

RW(1)

1. See the register description for more information.

0x00000000

4.3.3: Interrupt Control and State Register (ICSR)

on page 89.

0xE000ED08

VTOR RW

0x00000000

4.3.4: Vector Table Offset Register on page 91.

0xE000ED0C

AIRCR RW(1) 0xFA050000

4.3.5: Application Interrupt and Reset Control

0xE000ED10

SCR

0x00000000

4.3.6: System Control Register on page 92.

0xE000ED14

CCR

0x00000204

4.3.7: Configuration and Control Register on

page 93.

0xE000ED1C

SHPR

0x00000000

System Handler Priority Register 2 on page 94.

0xE000ED20

SHPR

0x00000000

System Handler Priority Register 3 on page 95.

IMPLEMENTER

VARIANT

Architecture

rrr

PART No

REVISION

rrr

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