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PM0223 bảng dữ liệu(PDF) 16 Page - STMicroelectronics

tên linh kiện PM0223
Giải thích chi tiết về linh kiện  This programming manual provides information for application and system-level software developers
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The STM32L0 Cortex-M0+ Processor
PM0223
16/110
DocID025763 Rev 1
See The condition flags on page 43 for more information about the APSR negative, zero,
carry or borrow, and overflow flags.
Interrupt Program Status Register
The IPSR contains the exception number of the current Interrupt Service Routine (ISR). See
the register summary in Table 3 on page 13 for its attributes. The bit assignments are:
Execution Program Status Register
The EPSR contains the Thumb state bit.
See the register summary in Table 3 on page 13 for the EPSR attributes. The bit assign-
ments are:
[28]
V
Overflow flag.
[27:0]
-
Reserved.
Table 6. IPSR bit assignments
Bits
Name
Function
[31:6]
-
Reserved
[5:0]
Exception number
This is the number of the current exception:
0 = Thread mode.
1 = Reserved.
2 = NMI.
3 = HardFault.
4-10 = Reserved.
11 = SVCall.
12, 13 = Reserved.
14 = PendSV.
15 = SysTick | Reserved.
16 = IRQ0.
.
.
47 = IRQ31.
48-63 = Reserved.
see Exception types on page 26 for more information.
Table 7. EPSR bit assignments
Bits
Name
Function
[31:25]
-
Reserved.
[24]
T
Thumb state bit.
[23:0]
-
Reserved.
Table 5. APSR bit assignment (continued)
Bits
Name
Description



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