PM0223 datasheet(98/110 Pages) STMICROELECTRONICS

98 / 110 page

STM32L0 Core Peripherals

PM0223

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DocID025763 Rev 1

4.4.5

SysTick usage hints and tips

The interrupt controller clock updates the SysTick counter. If this clock signal is stopped for

low power mode, the SysTick counter stops.

Ensure software uses word accesses to access the SysTick registers.

If the SysTick counter reload and current value are undefined at reset, the correct

initialization sequence for the SysTick counter is:

Program reload value.

Clear current value.

Program Control and Status register.

4.5

Memory Protection Unit

This section describes the Memory Protection Unit (MPU).

The MPU can divide the memory map into a number of regions, and defines the location,

size, access permissions, and memory attributes of each region. It supports:

•

Independent attribute settings for each region.

•

Overlapping regions.

•

Export of memory attributes to the system.

The memory attributes affect the behavior of memory accesses to the region. The STM32L0

Cortex-M0+ MPU defines:

•

Eight separate memory regions, 0-7.

•

A background region.

When memory regions overlap, a memory access is affected by the attributes of the region

with the highest number. For example, the attributes for region 7 take precedence over the

attributes of any region that overlaps region 7.

The background region has the same memory access attributes as the default memory

map, but is accessible from privileged software only.

The STM32L0 Cortex-M0+ MPU memory map is unified. This means instruction accesses

and data accesses have same region settings.

If a program accesses a memory location that is prohibited by the MPU, the processor

generates a HardFault exception.

In an OS environment, the kernel can update the MPU region setting dynamically based on

the process to be executed. Typically, an embedded OS uses the MPU for memory

protection.

Configuration of MPU regions is based on memory types, see 2.2.1: Memory regions, types

and attributes on page 20.

Table 34 on page 99 shows the possible MPU region attributes. These include Shareability

and cache behavior attributes that are not relevant to most microcontroller implementations.

See MPU configuration for a microcontroller on page 107 for guidelines for programming

such an implementation.

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