AS3517H-ECTP datasheet(47/94 Pages) AMSCO

47 / 94 page

AS3517 V17

Data Sheet, Confidential

www.austriamicrosystems.com

9.3

SYSTEM Functions

9.3.1

SYSTEM

General

The system block handles the power up, power down and regulator voltage settings of the AFE.

Power Up Conditions

The chip powers up when on of the following condition is true:

•

High signal on the PWR_UP pin (>80ms, >1V & >1/3 BVDD)

•

Rising edge on the VBUS pin (USB plug in: >80ms, BVDD>3V, VBUS>4.5V)

•

Rising edge on the CHGIN pin (charger plug in: >80ms, BVDD>3V, CHGIN>4.0V)

•

Rising edge on the RTCSUP and consequently on RVDD pin (RTCSUP > 1.35V, BVDD >3V)

•

RTC wake-up: The auto wake-up timer is internally connected to the Power-up and Hibernation Control block.

To hold the chip in power up mode the PWR_HOLD bit in the SYSTEM register (0x20h) is set.

Power Down Conditions

The chip automatically shuts off if one of the following conditions arises:

•

Clearing the PWR_HOLD bit in SYSTEM register (0x20h)

•

I2C watchdog power down(no serial reading for >1s, has to be enabled)

•

Heartbeat watchdog via pin HBT(no watchdog reset via HBT pin for > 500ms, has to be enabled)

Please note, that when using power-up sequence 16 to 25 no power down is performed but a reset puls (86us typ,

60us min) will be performed.

•

BVDD drops below the minimum threshold voltage (<2.7V)

•

LDO or step down converter output voltage drop below a programmable level (has to be enabled)

•

Junction temperature reaches maximum threshold, set in SUPERVISOR register (0x24h)

•

High signal on the PWR_UP pin for more than (>5.4s, >1V & >1/3 BVDD).

With setting SD_TIME bit in register 24h the time can be doubled.

Revision 1v3

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