AS3517H-ECTP datasheet(80/94 Pages) AMSCO

80 / 94 page

AS3517 V17

Data Sheet, Confidential

www.austriamicrosystems.com

Table 82 I2S_PLL_OSC Register

Name

Base

Default

I2S_PLL_OSC

2-wire serial

00h

I2S, PLL and Oscillator Mode Control Registers

Offset: 1Dh

This register is reset at a DVDD-POR.

Bit

Bit Name

Default

Access

Bit Description

I2S_MASTER_ON

R/W

Switched the I2S master mode on

0: I2S slave mode operation

1: I2S master mode

OSC24_PD

R/W

Powers the 12-24MHz oscillator down. For operation a 12-

24MHz crystal needs to be connected to pins XIN24/XOUT24.

0: 12-24MHz oscillator enabled

1: powered down

I2S_DIRECT

R/W

Switches the PWGD pin to an input for an external master

clock (e.g. coming form the CPU). This bit overwrites prior

setting for the PWGD pin. Only valid fro I2S slave mode

operation.

0: disabled

1: enabled

4:3

Q24M_DIVIDER

R/W

Sets the divider for Q24M clock output or powers Q24M clock

output buffer down

00: divide by 1

01:divide by 2

10:divide by 4

11: OFF

2:1

PLL_MODE

R/W

Preset of PLL bias for the following sampling frequencies

00: reserved

01:16-48kS

10: 8-12kS

11: reserved

I2S_DIVIDER_8

R/W

Bit 8 of I2S_DIVIDER (Reg. 1Ch)

Please see master clock divider table

Revision 1v3

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