AS3517H-ECTP datasheet(25/94 Pages) AMSCO

25 / 94 page

AS3517 V17

Data Sheet, Confidential

www.austriamicrosystems.com

via pin PWGD

Power Save Options

The bias current of the DAC block can be reduced in three steps down to 50% to reduce the power consumption.

Clock Supervision

The digital audio interface automatically checks the LRCLK. An interrupt can be generated when the state of the LRCLK input changes. A

bit in the interrupt register represents the actual state (present or not present) of the LRCLK.

Signal Description

The digital audio interface uses the standard I2S format:

•

left justified

•

MSB first

•

one additional leading bit

The first 18 bits are taken for DAC conversion. The on-chip synchronization circuit allows any bit-count up 32bit. When there are less than

18 bits sampled, the data sample is completed with “0”s. In I2S direct mode the data length has to be minimum 18 bits.

The ADC output is always 20 bit. If more SCLK pulses are provided, only the first 20 will be significant. All following bits will be “0”.

SCLK has not to be necessarily synchronous to LRCLK but the high going edge has to be separate from LRCLK edges. The LRCK signal

has to be derived from a jitter-free clock source, because the on-chip PLL is generating a clock for the digital filter, which has to be always

in correct phase lock condition to the external LRCLK.

Please observe that in slave mode LRCLK has to be activated before enabling the ADC.

In Master Mode operation SCLK has 32 clock cycles for each sample word.

256

LRCK

LRCLK

MCLK

SCLK

Sample Rates

In Master Mode AS3517 allows programming various sample rates. The master clock is generated by the 12-24MHz oscillator. Sampling

frequencies from 8kHz to 48kHz can be selected. For certain division ratios between master clock and sample ratio a certain deviation is

system inherent.

)

(

PLLMode

LRCLK

OSC

)

511

(

.......

..........

)

(

......

..........

−

RateDivide

factor

PLL

PLLMode

frequency

lator

Quarzoscil

osc

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