PIC18F2680ISPSQTP datasheet(115/482 Pages) MICROCHIP

115 / 482 page

Preliminary

DS39625C-page 113

PIC18F2585/2680/4585/4680

9.0

INTERRUPTS

The PIC18F2585/2680/4585/4680 devices have multi-

ple interrupt sources and an interrupt priority feature

that allows each interrupt source to be assigned a high

priority level or a low priority level. The high priority

interrupt vector is at 000008h and the low priority

interrupt vector is at 000018h. High priority interrupt

events will interrupt any low priority interrupts that may

be in progress.

There are ten registers which are used to control

interrupt operation. These registers are:

• RCON

•INTCON

• INTCON2

• INTCON3

• PIR1, PIR2, PIR3

• PIE1, PIE2, PIE3

• IPR1, IPR2, IPR3

It is recommended that the Microchip header files

supplied with MPLAB® IDE be used for the symbolic bit

names in these registers. This allows the assembler/

compiler to automatically take care of the placement of

these bits within the specified register.

Each interrupt source has three bits to control its

operation. The functions of these bits are:

• Flag bit to indicate that an interrupt event

occurred

• Enable bit that allows program execution to

branch to the interrupt vector address when the

flag bit is set

• Priority bit to select high priority or low priority

The interrupt priority feature is enabled by setting the

IPEN bit (RCON<7>). When interrupt priority is

enabled, there are two bits which enable interrupts

globally. Setting the GIEH bit (INTCON<7>) enables all

interrupts that have the priority bit set (high priority).

Setting the GIEL bit (INTCON<6>) enables all

interrupts that have the priority bit cleared (low priority).

When the interrupt flag, enable bit and appropriate

global interrupt enable bit are set, the interrupt will

vector immediately to address 000008h or 000018h,

depending on the priority bit setting. Individual inter-

rupts can be disabled through their corresponding

enable bits.

When the IPEN bit is cleared (default state), the inter-

rupt priority feature is disabled and interrupts are com-

patible with PIC® mid-range devices. In Compatibility

mode, the interrupt priority bits for each source have no

effect. INTCON<6> is the PEIE bit, which enables/

disables all peripheral interrupt sources. INTCON<7>

is the GIE bit, which enables/disables all interrupt

sources. All interrupts branch to address 000008h in

Compatibility mode.

When an interrupt is responded to, the global interrupt

enable bit is cleared to disable further interrupts. If the

IPEN bit is cleared, this is the GIE bit. If interrupt priority

levels are used, this will be either the GIEH or GIEL bit.

High priority interrupt sources can interrupt a low

priority interrupt. Low priority interrupts are not

processed while high priority interrupts are in progress.

The return address is pushed onto the stack and the

PC is loaded with the interrupt vector address

(000008h or 000018h). Once in the Interrupt Service

Routine, the source(s) of the interrupt can be deter-

mined by polling the interrupt flag bits. The interrupt

flag bits must be cleared in software before re-enabling

interrupts to avoid recursive interrupts.

The “return from interrupt” instruction, RETFIE, exits

the interrupt routine and sets the GIE bit (GIEH or GIEL

if priority levels are used), which re-enables interrupts.

For external interrupt events, such as the INT pins or

the PORTB input change interrupt, the interrupt latency

will be three to four instruction cycles. The exact

latency is the same for one or two-cycle instructions.

Individual interrupt flag bits are set, regardless of the

status of their corresponding enable bit or the GIE bit.

Note:

Do not use the MOVFF instruction to modify

any of the interrupt control registers while

any interrupt is enabled. Doing so may

cause erratic microcontroller behavior.

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