PIC18F2680ISPSQTP datasheet(262/482 Pages) MICROCHIP

262 / 482 page

PIC18F2585/2680/4585/4680

DS39625C-page 260

Preliminary

FIGURE 20-3:

COMPARATOR OUTPUT BLOCK DIAGRAM

20.6

Comparator Interrupts

The comparator interrupt flag is set whenever there is

a change in the output value of either comparator.

Software will need to maintain information about the

status of the output bits, as read from CMCON<7:6>, to

determine the actual change that occurred. The CMIF

bit (PIR2<6>) is the Comparator Interrupt Flag. The

CMIF bit must be reset by clearing it. Since it is also

possible to write a ‘1’ to this register, a simulated

interrupt may be initiated.

Both the CMIE bit (PIE2<6>) and the PEIE bit

(INTCON<6>) must be set to enable the interrupt. In

addition, the GIE bit (INTCON<7>) must also be set. If

any of these bits are clear, the interrupt is not enabled,

though the CMIF bit will still be set if an interrupt

condition occurs.

The user, in the Interrupt Service Routine, can clear the

interrupt in the following manner:

Any read or write of CMCON will end the

mismatch condition.

Clear flag bit CMIF.

A mismatch condition will continue to set flag bit CMIF.

Reading CMCON will end the mismatch condition and

allow flag bit CMIF to be cleared.

20.7

Comparator Operation

During Sleep

When a comparator is active and the device is placed

in Sleep mode, the comparator remains active and the

interrupt is functional if enabled. This interrupt will

wake-up the device from Sleep mode, when enabled.

While the comparator is powered up, higher Sleep

currents than shown in the power-down current

specification will occur. Each operational comparator

will consume additional current, as shown in the

comparator

specifications.

minimize

power

consumption while in Sleep mode, turn off the

comparators (CM2:CM0 = 111) before entering Sleep.

If the device wakes up from Sleep, the contents of the

CMCON register are not affected.

20.8

Effects of a Reset

A device Reset forces the CMCON register to its Reset

state, causing the comparator module to be in the Com-

parator Reset mode (CM2:CM0 = 000). This ensures

that all potential inputs are analog inputs. Device

current is minimized when analog inputs are present at

Reset time. The comparators are powered down during

the Reset interval.

To RE1 or

RE2 pin

Bus

Data

Set

CMIF

bit

Port pins

Read CMCON

Reset

From

other

Comparator

CxINV

Note:

If a change in the CMCON register

(C1OUT or C2OUT) should occur when a

read operation is being executed (start of

the Q2 cycle), then the CMIF (PIR

registers) interrupt flag may not get set.

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