OR3LP26B datasheet(144/184 Pages) AGERE

144 / 184 page

ORCA OR3LP26B FPSC

Data Sheet

Embedded Master/Target PCI Interface

March 2000

144

Lucent Technologies Inc.

Timing Characteristics (continued)

Table 60. OR3LP26B FPGA to PCI, and PCI to FPGA, Combinatorial Path Delays

OR3LP26B Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C; VDD2 = 2.38 V to 2.63 V, 0 °C < TA < 70 °C.

Notes:

The FPGA to PCI combinatorial path delays include the ASIC path delay and the output buffer delay under a 10 pF load. They do not include the

interbuf delay on the FPGA side.

The PCI to FPGA combinatorial path delays include the ASIC input buffer delay, and ASIC path delay entering the FPGA. They do not include

the interbuf delay on the FPGA side.

Table 61. OR3LP26B FPGA Side Interface Combinatorial Path Delay Signals

OR3LP26B Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C; VDD2 = 2.38 V to 2.63 V, 0 °C < TA < 70 °C.

Note: The combinatorial path parameters are measured from the input to the output (both on the FPGA side), excluding the interbufs, which

traverse the ASIC/FPGA boundary. The

ORCA Foundry Static Analysis Tool, Trace, accounts for clock skew and interbuf delays on the

clock and data paths.

Description (TI = 85 °C, VDD = min, VDD2 = min)

Min

Max

Unit

Source

Destination

pci_intan (FPGA side)

intan (PCI side)

—

4.094

clk (PCI side)

pciclk (FPGA side)

—

3.226

rstn (PCI side)

pci_rstn (FPGA side)

—

1.622

Description (TI = 85 °C, VDD = min, VDD2 = min)

Min

Max

Unit

Source

Destination

fifo_sel

datatofpga[63:0]

—

3.253

fifo_sel

datatofpgax[7:0]

—

2.652

twdataenn

twlastcycn

—

5.220

twdataenn

datatofpga[63:0] (dual-

port mode)

—

6.114

twdataenn

datatofpgax[7:0] (dual-

port mode)

—

5.847

twdataenn

twdata[35:0] (quad-port

mode)

—

6.114

trdataenn

trlastcycn

—

5.558

mrdataenn

mrlastcycn

—

5.237

taenn

twlastcycn

—

5.406

taenn

tstatecntr[2:0]

—

4.767

taenn

datatofpga[63:0] (dual-

port mode)

—

5.944

taenn

datatofpgax[7:0] (dual-

port mode)

—

5.763

taenn

twdata[35:0] (quad-port

mode)

—

5.944

taenn

treqn

—

4.958

maenn

mstatecntr[2:0]

—

5.860

mcmd

mstatecntr[2:0]

—

5.662

tcfgshiftenn

pci_tdfg_stat

—

4.227

mcfgshiftenn

pci_mdfg_stat

—

5.300

OR3LP26B bảng dữ liệu(PDF) 144 Page - Agere Systems

OR3LP26B bảng dữ liệu(HTML) 144 Page - Agere Systems

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL