OR3LP26B datasheet(15/184 Pages) AGERE

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Lucent Technologies Inc.

Data Sheet

ORCA OR3LP26B FPSC

March 2000

Embedded Master/Target PCI Interface

Lucent Technologies Inc.

PCI Bus Core Detailed Description (continued)

Table 4. PCI Bus Command Descriptions (continued)

Command

Code

(Binary

)

Command

Master

Generates

Target

Accepts

Description

0111

Memory

Write

√√

Fully implemented.

Target: Writes are posted, bursting is allowed, and no wait-states

are generated.

Master: Bursting is allowed, and no wait-states are generated.

1000

(reserved)

—

Target ignores, per PCI Specification section 3.1.1.

1001

(reserved)

—

Target ignores, per PCI Specification section 3.1.1.

1010

Configura-

tion Read

√√

Fully implemented.

Target: Bursting is disallowed, and no wait-states are generated.

Target disconnects with data on first data word. The FPGA portion

of the device is not involved in Target configuration transactions.

Master: Bursting is allowed, and no wait-states are generated.

1011

Configura-

tion Write

√√

Fully implemented.

Target: Bursting is disallowed, and no wait-states are generated.

Target disconnects with data on first data word. The FPGA portion

of the device is not involved in Target configuration transactions.

Master: Bursting is allowed, and no wait-states are generated.

1100

Memory

Read

Multiple

√√

Fully implemented. Both the Master and the Target treat this

instruction the same as a memory read (0110); the user’s FPGA

logic is responsible for ensuring that the Master operation meets

the special requirement that the read request ends on a cacheline

boundary.

1101

Dual

Access

Cycle

√√

Fully implemented. Per PCI Specification section 3.9, the PCI core

will automatically convert a 64-bit address to a 32-bit address if

the upper 32 bits are all zeros.

1110

Memory

Read Line

√√

Fully implemented. Both the Master and the Target treat this

instruction the same as a memory read (0110); the user’s FPGA

logic is responsible for ensuring that the Master operation meets

the special requirement that the read request continues to the next

cacheline boundary.

1111

Memory

Write and

Invalidate

√√

Fully implemented. Both the Master and the Target treat this

instruction the same as a memory write (0111); the user’s FPGA

logic is responsible for ensuring that the Master operation meets

the special requirement that writes of complete cachelines, with all

byte enables, are performed.

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