OR3LP26B datasheet(98/184 Pages) AGERE

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Giải thích chi tiết về linh kiện	Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface

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ORCA OR3LP26B FPSC

Data Sheet

Embedded Master/Target PCI Interface

March 2000

Lucent Technologies Inc.

PCI Bus Core Detailed Description Quad Port (continued)

Master Read, Burst Transaction

Figure 32 (FPGA bus) and Figure 31 (PCI bus) show the timing of a four Quadword Master read burst. Operation is

similar to that in the Master read, nonburst transaction, but extra data words are supplied by the FPGA application.

In Figure 32, the transaction is initiated by the FPGA application asserting Master address enable (maenn), while

providing the command and burst length on bus mwdata. On the next clock, the FPGA application provides the

DWORD address and asserts mwlastcycn. On the third cycle, both maenn and mwlastcycn are deasserted. PCI

bus activity now begins as shown in Figure 31. Once data is transferred on the PCI bus and mr_emptyn is deas-

serted high, the FPGA application asserts mrdataenn and eight DWORDs of data are transferred on bus mrdata.

5-8850(F).a

Figure 31. Master Read 32-Byte Burst (PCI Bus, 64-Bit)

ADRS

CMD

BE0

BE1

BE2

BE3

clk

framen

c_ben

irdyn

trdyn

stopn

irdyn

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