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OR3LP26B bảng dữ liệu(PDF) 38 Page - Agere Systems |
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OR3LP26B bảng dữ liệu(HTML) 38 Page - Agere Systems |
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38 / 184 page  ORCA OR3LP26B FPSC Data Sheet Embedded Master/Target PCI Interface March 2000 38 Lucent Technologies Inc. Lucent Technologies Inc. PCI Bus Core Detailed Description Dual Port (continued) Master Write, Nonburst Transaction Figure 2 (FPGA bus) and Figure 3 (PCI bus) show the timing of a Master write, nonburst transaction. In Figure 2, the transaction is initiated by the FPGA application asserting Master address enable (maenn), while providing the command word and the address on bus datafmfpga. On the next clock, maenn is deasserted and the one Quad- word of data is provided on bus datafmfpga along with assertion of the Master write data enable (mwdataenn). Since the protocol for providing start-up data is fixed for a specific operation, the FPGA application can be prepro- grammed with the sequence, or can use the value of the Master state counter (mstatecntr) to assist in determina- tion of the next required data word of information. The PCI core knows that this is a nonburst operation because the FPGA application asserts the Master write burst signal (mwlastcycn). This completes the setup for this operation. Execution begins on the PCI bus, as shown in Figure 3. 5-88831(F).a Figure 2. Master Write Single (FPGA Bus, Dual-Port) T0 T1 T2 T3 T4 X 0 4 0 X CMD X X ADRS D0 X fclk ma_fulln mstatecntr mcmd datafmfpga maenn mwdataenn mwlastcycn mw_fulln mw_afulln mwpcihold |
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