công cụ tìm kiếm bảng dữ liệu linh kiện điện tử
  Vietnamese  ▼
ALLDATASHEET.VN

X  

Preview PDF HTML

OR3LP26B bảng dữ liệu(PDF) 46 Page - Agere Systems

tên linh kiện OR3LP26B
Giải thích chi tiết về linh kiện  Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface
PDF  184 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
nhà sản xuất  AGERE [Agere Systems]
Trang chủ  
Logo AGERE - Agere Systems

OR3LP26B bảng dữ liệu(HTML) 46 Page - Agere Systems

Back Button OR3LP26B Datasheet HTML 42Page - Agere Systems OR3LP26B Datasheet HTML 43Page - Agere Systems OR3LP26B Datasheet HTML 44Page - Agere Systems OR3LP26B Datasheet HTML 45Page - Agere Systems OR3LP26B Datasheet HTML 46Page - Agere Systems OR3LP26B Datasheet HTML 47Page - Agere Systems OR3LP26B Datasheet HTML 48Page - Agere Systems OR3LP26B Datasheet HTML 49Page - Agere Systems OR3LP26B Datasheet HTML 50Page - Agere Systems Next Button
Zoom Inzoom in Zoom Outzoom out
 46 / 184 page
background image
ORCA OR3LP26B FPSC
Data Sheet
Embedded Master/Target PCI Interface
March 2000
46
Lucent Technologies Inc.
Lucent Technologies Inc.
PCI Bus Core Detailed Description Dual Port (continued)
Master Read, Burst Transaction
Figure 8 (FPGA bus dual port) and Figure 9 (PCI bus) show the timing of a four Quadword Master read burst. Oper-
ation is similar to that in the Master read, nonburst transaction, but extra data words are supplied by the FPGA
application. In Figure 8, the transaction is initiated by the FPGA application asserting Master address enable
(maenn), while providing the command, burst length, and lower DWORD address on bus datafmfpga. On the next
clock, the FPGA application provides the upper DWORD address and asserts mwlastcycn. On the third cycle,
both maenn and mwlastcycn are deasserted. PCI bus activity now begins as shown in Figure 9. Once data is
transferred on the PCI bus and mr_emptyn is deasserted high, the FPGA application asserts mrdataenn and four
Quadwords of data are transferred on bus datatofpga.
5-8834(F).a
Figure 8. Master Read 32-Byte Burst (FPGA Bus, Dual-Port, Burst Length, and 64-Bit Address)
T0
T1
T2
T3
T4
TN
TN+1
TN+2
TN+3
TN+4
TN+5
TN+6
X
0
1
4
4
0
X
CMD
X
X
X
BRST
ADRS
X
X
X
X
D0
D1
D2
D3
X
fclk
ma_fulln
mstatecntr
mcmd
datafmfpga
datatofpga
maenn
mrdataenn
mwlastcycn
mrlastcycn
mr_emptyn
mr_aemptyn



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


bảng dữ liệu tải về

Go To PDF Page


Link URL



Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không?  [ DONATE ] 

Alldatasheet là   |   Quảng cáo   |   Liên lạc với chúng tôi   |   Chính sách bảo mật   |   Liên kết đến bảng dữ liệu    |   Trao đổi link   |   Tìm kiếm theo nhà sản xuất
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com