OR3LP26B datasheet(64/184 Pages) AGERE

64 / 184 page

ORCA OR3LP26B FPSC

Data Sheet

Embedded Master/Target PCI Interface

March 2000

Lucent Technologies Inc.

PCI Bus Core Detailed Description Dual Port (continued)

Target Read Memory, Nonburst, Delayed Transaction

Figure 19 (PCI bus) and Figure 20 (FPGA bus) show the timing for a Target memory nonburst read handled as a

delayed transaction. The FPGA application indicates its desire to do this by asserting signal deltrn. The timing on

the PCI interface (Figure 19) is similar to that of an I/O read (Figure 17) except that stop is not asserted here to

cause disconnect with data, but rather the operation is free to continue since it is allowed to complete on the source

(PCI) bus before it completes on the destination (FPGA) bus. The FPGA interface timing is as shown in Figure 20

and is the same as the timing in the I/O accesses of Target I/O read, delayed transaction and Target I/O read, no

delayed transaction.

5-8860(F).a

Figure 19. Target Memory Single Read, Delayed (PCI Bus, 64-Bit)

Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tb6 Tc0

Tc1

Tc2

Tc3

Tc4

Tc5

Tc6

ADRS

DATA

CMD

BEs

CMD

BEs

CMD

BEs

clk

framen

c_ben

irdyn

devseln

trdyn

stopn

TRANSACTION #1: ADDRESS, BYTE ENABLES,

AND COMMAND LATCHED AS A

DELAYED READ REQUEST.

TRANSACTION #2: DISCONNECTED W/O DATA

BECAUSE READ OPERATION NOT COMPLETED.

TRANSACTION #3: NORMAL COMPLETION

BECAUSE READ OPERATION COMPLETED.

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