OR3LP26B datasheet(147/184 Pages) AGERE

147 / 184 page

Lucent Technologies Inc.

147

Data Sheet

ORCA OR3LP26B FPSC

March 2000

Embedded Master/Target PCI Interface

Lucent Technologies Inc.

Timing Characteristics (continued)

Table 65. OR3LP26B FPGA Side Interface Input Setup Delays, pciclk Synchronous Signals

OR3LP26B Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C; VDD2 = 2.38 V to 2.63 V, 0 °C < TA < 70 °C.

Note: The input setup parameters are measured from the pciclk clock output pin on the FPGA side, excluding the interbufs, which traverse the

ASIC/FPGA boundary. The

ORCA Foundry Static Analysis Tool, Trace, accounts for clock skew and interbuf delays on the clock and data

paths.

Table 66. OR3LP26B FPGA Side Interface Input Setup Delays, fclk Synchronous Signals

OR3LP26B Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C; VDD2 = 2.38 V to 2.63 V, 0 °C < TA < 70 °C.

Note: The input setup parameters are measured from the FCLK1 and FCLK2 clock input pins on the FPGA side, excluding the interbufs, which

traverse the ASIC/FPGA boundary. The

ORCA Foundry Static Analysis Tool, Trace, accounts for clock skew and interbuf delays on the

clock and data paths.

Description (TI = 85 °C, VDD = min, VDD2 = min)

Min

Max

Unit

fpga_mbusyn

–0.514

—

deltrn

–1.486

—

mwpcihold

–1.190

—

fpga_mstopburstn

–1.208

—

fpga_tabort

1.744

—

fpga_tretryn

0.864

—

twburstpendn

–1.561

—

trpcihold

–1.542

—

trburstpendn

–1.557

—

fpga_syserror

–0.828

—

Description (TI = 85 °C, VDD = min, VDD2 = min)

Min

Max

Unit

mcfgshiftenn

1.752

—

maenn

4.777

—

mfifoclrn

5.934

—

mcmd[3:0]

5.251

—

mwdataenn

4.806

—

datafmfpga[63:0] (dual-port mode)

5.333

—

datafmfpgax[7:0] (dual-port mode)

5.978

—

mwdata[35:0] (quad-port mode)

5.978

—

trdata[35:0] (quad-port mode)

5.226

—

mwlastcycn

4.896

—

mrdataenn

3.246

—

tcfgshiftenn

1.209

—

tfifoclrn

3.395

—

taenn

3.893

—

twdataenn

3.677

—

trdataenn

3.773

—

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