OR3LP26B datasheet(142/184 Pages) AGERE

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ORCA OR3LP26B FPSC

Data Sheet

Embedded Master/Target PCI Interface

March 2000

142

Lucent Technologies Inc.

Timing Characteristics (continued)

Table 57. OR3LP26B Input to Fast Clock Setup/Hold Time (Pin-to-Pin)

OR3LP26B Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C; VDD2 = 2.38 V to 2.63 V, 0 °C < TA < 70 °C.

Notes:

The pin-to-pin timing parameters in this table should be used instead of results reported by

ORCA Foundry.

The fclk delays are for a fully routed clock tree that uses the ExpressCLK input into the fast clock network. It includes both the input buffer delay

and the clock routing to the PFU CLK input. The delay will be reduced if any of the clock branches are not used.

5-4847(F).a

Figure 55. Input to Fast Clock Setup/Hold Time

Description

(TJ = 85 °C, VDD = min)

Min

Max

Unit

Output Not on Same Side of Device As Input Clock (Fast Clock Delays Using ExpressCLK Inputs)

Input to fclk Setup Time (middle ECLK pin)

0.0

—

Input to fclk Setup Time (middle ECLK pin, delayed data input)

5.58

—

Input to fclk Setup Time (corner ECLK pin)

0.0

—

Input to fclk Setup Time (corner ECLK pin, delayed data input)

3.77

—

Input to fclk Hold Time (middle ECLK pin)

4.62

—

Input to fclk Hold Time (middle ECLK pin, delayed data input)

0.0

—

Input to fclk Hold Time (corner ECLK pin)

6.54

—

Input to fclk Hold Time (corner ECLK pin, delayed data input)

0.0

—

ECLK

INPUT

PIO FF

CLKCNTRL

fclk

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