MPC8569E datasheet(107/127 Pages) FREESCALE

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Enhanced Local Bus Controller

MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

107

The following figure shows the AC timing diagram for PLL bypass mode.

Figure 59. Enhanced Local Bus Signals (PLL Bypass Mode)

The above figure applies to all three controllers that eLBC supports: GPCM, UPM, and FCM.

For input signals, the AC timing data is used directly for all three controllers.

For output signals, each type of controller provides its own unique method to control the signal timing. The final signal delay

value for output signals is the programmed delay plus the AC timing delay. For example, for GPCM, LCS can be programmed

to delay by tacs (0, ¼, ½, 1, 1 + ¼, 1 + ½, 2, 3 cycles), so the final delay is tacs + tLBKHOV.

Output Signals

tLBKLOX

LCLK[m]

Input Signals

LALE

tLBIXKH

tLBIVKH

tLBIVKL

tLBIXKL

Input Signal

tLBONOT

(LUPWAIT/LFRB)

(Except LUPWAIT/LFRB)

(Except LALE)

LAD

(address phase)

LAD/LDP

(data phase)

tLBKLOZ

tLBKLOV

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