MPC8569E datasheet(62/127 Pages) FREESCALE

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MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Ethernet Interface

Freescale Semiconductor

The following figure provides the AC test load.

Figure 23. AC Test Load

The following figure shows the TBI receive AC timing diagram.

Figure 24. TBI Receive AC Timing Diagram

RCG[9:0] hold time to rising PMA_RX_CLK

tTRDXKH

1.5

—

PMA_RX_CLK[0:1] clock rise time (20%–80%)

tTRXR

0.7

—

2.4

PMA_RX_CLK[0:1] clock fall time (80%–20%)

tTRXF

0.7

—

2.4

Note:

1. The frequency of RX_CLK should not exceed the frequency of gigabit Ethernet reference clock by more than 300 ppm.

2. System/board must be designed to ensure the input requirement to the device is achieved. Proper device operation is

guaranteed for inputs meeting this requirement by design, simulation, characterization, or functional testing.

Table 33. TBI Receive AC Timing Specifications (continued)

For recommended operating conditions, see Table 3

Parameter

Symbol

Min

Typ

Max

Unit

Note

Output

Z0 = 50 Ω

LVDD/2

RL = 50 Ω

PMA_RX_CLK1

RCG[9:0]

tTRX

tTRXH

tTRXR

tTRXF

tTRDVKH

PMA_RX_CLK0

tTRDXKH

tTRDVKH

tTRDXKH

tSKTRX

tTRXH

Valid Data

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