MPC8569E datasheet(41/127 Pages) FREESCALE

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Overall DC Electrical Characteristics

MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

The following table provides the PLL lock times.

Maximum rise/fall time of HRESET

—

SYSCLK

Minimum assertion time for SRESET

—

SYSCLK

PLL input setup time with stable SYSCLK before HRESET negation

—

SYSCLK

—

Input setup time for POR configurations (other than PLL configuration)

with respect to negation of HRESET

—

SYSCLK

Input hold time for all POR configurations (including PLL configuration)

with respect to negation of HRESET

—

SYSCLK

Maximum valid-to-high impedance time for actively driven POR

configurations with respect to negation of HRESET

—

SYSCLK

Note:

1. There may be some extra current leakage when driving signals high during this time.

2. Reset assertion timing requirements for DDR3 DRAMs may differ.

3. TRST is an asynchronous level sensitive signal. For guidance on how this requirement can be met, refer to the JTAG signal

termination guidelines in AN4232 MPC8569E PowerQUICC III Design Checklist.

4. SYSCLK is the primary clock input for the MPC8569E.

5. System/board must be designed to ensure the input requirement to the device is achieved. Proper device operation is

guaranteed for inputs meeting this requirement by design, simulation, characterization, or functional testing.

Table 6. PLL Lock Times

Parameter

Min

Max

Unit

Core PLL lock time

—

100

μs

Platform PLL lock time

—

100

μs

QUICC Engine block PLL lock time

—

100

μs

DDR PLL lock times

—

100

μs

Table 5. RESET Initialization Timing Specifications (continued)

Parameter

Min

Max

Unit

Notes

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