MPC8569E datasheet(53/127 Pages) FREESCALE

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DUART

MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

The following figure provides the AC test load for the DDR2 and DDR3 controller bus.

Figure 11. DDR2 and DDR3 Controller Bus AC Test Load

2.5

DUART

This section describes the DC and AC electrical specifications for the DUART interface of the MPC8569E.

2.5.1

DUART DC Electrical Characteristics

The following table provides the DC electrical characteristics for the DUART interface.

2.5.2

DUART AC Electrical Specifications

The following table provides the AC timing parameters for the DUART interface.

Table 21. DUART DC Electrical Characteristics

For recommended operating conditions, see Table 3

Parameter

Symbol

Min

Max

Unit

Notes

Input high voltage

VIH

2—

Input low voltage

VIL

—0.8

Input current (OVIN = 0 V or OVIN = OVDD)IIN

—±40

μA2

Output high voltage (OVDD = mn, IOH = –2 mA)

VOH

2.4

—

Output low voltage (OVDD = min, IOL = 2 mA)

VOL

—0.4

—

Note:

1. The min VILand max VIH values are based on the min and max OVIN respective values found in Table 3.

2. The symbol OVIN represents the input voltage of the supply. It is referenced in Table 3.

Table 22. DUART AC Timing Specifications

For recommended operating conditions, see Table 3

Parameter

Value

Unit

Notes

Minimum baud rate

fCCB/1,048,576

baud

Maximum baud rate

fCCB/16

baud

1, 2

Oversample rate

—

Notes:

1. fCCB refers to the internal platform clock.

2. The actual attainable baud rate is limited by the latency of interrupt processing.

3. The middle of a start bit is detected as the 8th sampled 0 after the 1-to-0 transition of the start bit. Subsequent bit values are

sampled each 16th sample.

Output

Z0 = 50 Ω

GVDD/2

RL = 50 Ω

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