MPC8569E datasheet(48/127 Pages) FREESCALE

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MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

DDR2 and DDR3 SDRAM Controller

Freescale Semiconductor

2.4.2

DDR2 and DDR3 SDRAM Interface AC Timing Specifications

This section provides the AC timing specifications for the DDR SDRAM controller interface. The DDR controller supports both

DDR2 and DDR3 memories. Note that the required GVDD(typ) voltage is 1.8 V or 1.5 V when interfacing to DDR2 or DDR3

SDRAM respectively.

2.4.2.1

DDR2 and DDR3 SDRAM Interface Input AC Timing Specifications

The following table provides the input AC timing specifications for the DDR controller when interfacing to DDR2 SDRAM.

The following table provides the input AC timing specifications for the DDR controller when interfacing to DDR3 SDRAM.

The following table provides the input AC timing specifications for the DDR controller when interfacing to DDR2 and DDR3

SDRAM.

Table 17. DDR2 SDRAM Interface Input AC Timing Specifications

At recommended operating conditions with GVDD of 1.8 V ± 5%

Parameter

Symbol

Min

Max

Unit

Notes

AC input low voltage

> 533 MHz data rate

VILAC

—MVREFn – 0.20

—

≤ 533 MHz data rate

—

MVREFn – 0.25

AC input high voltage

> 533 MHz data rate

VIHAC

MVREFn + 0.20

—

≤ 533 MHz data rate

MVREFn + 0.25

—

Table 18. DDR3 SDRAM Interface Input AC Timing Specifications

At recommended operating conditions with GVDD of 1.5 V ± 5%

Parameter

Symbol

Min

Max

Unit

Notes

AC input low voltage

VILAC

—

MVREFn – 0.175

—

AC input high voltage

VIHAC

MVREFn + 0.175

—

Table 19. DDR2 and DDR3 SDRAM Interface Input AC Timing Specifications3

At recommended operating conditions with GVDD of 1.8 V ± 5% for DDR2 or 1.5 V ± 5% for DDR3

Parameter

Symbol

Min

Max

Unit

Note

Controller Skew for MDQS—MDQ/MECC

tCISKEW

——

800 MHz data rate

–200

200

667 MHz data rate

–240

240

533 MHz data rate

–300

300

400 MHz data rate

–365

365

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