MPC8569E datasheet(103/127 Pages) FREESCALE

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Enhanced Local Bus Controller

MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

103

2.15.2.2

Enhanced Local Bus AC Timing Specifications for PLL Enable Mode

For PLL enable mode, all timings are relative to the rising edge of LSYNC_IN.

The following table describes the timing specifications of the enhanced local bus interface at BVDD = 3.3 V, 2.5 V and 1.8 V

for PLL enable mode.

Table 66. Enhanced Local Bus Timing Specifications (BVDD = 3.3 V 2.5 V and 1.8 V) —PLL Enabled Mode

For recommended operating conditions, see Table 3

Parameter

Symbol1

Min

Max

Unit

Notes

Enhanced local bus cycle time

tLBK

7.5

—

Enhanced local bus duty cycle

tLBKH/tLBK

LCLK[n] skew to LCLK[m] or LSYNC_OUT

tLBKSKEW

—

680

Input setup

tLBIVKH

2—

—

Input hold

tLBIXKH

1.0

—

Output delay

(Except LALE)

tLBKHOV

—3.8

—

Output hold

(Except LALE)

tLBKHOX

0.6

—

Enhanced local bus clock to output high

impedance for LAD/LDP

tLBKHOZ

—3.8

LALE output negation to LAD/LDP output

transition (LATCH hold time)

tLBONOT

1 – 0.475 ns

(LBCR[AHD]=0)

½ – 0.475 ns

(LBCR[AHD] = 1)

—

eLBC controller

clock cycle

(= 1 platform

clock cycle in

ns)

Notes:

1. All signals are measured from BVDD/2 of the rising edge of LSYNC_IN to BVDD/2 of the signal in question.

2. Skew measured between different LCLK signals at BVDD/2.

3. For purposes of active/float timing measurements, the high impedance or off state is defined to be when the total current

delivered through the component pin is less than or equal to the leakage current specification.

4. tLBONOT is a measurement of the minimum time between the negation of LALE and any change in LAD. tLBONOT is determined

by LBCR[AHD]. The unit is the eLBC controller clock cycle. The eLBC controller clock refers to the internal clock that runs the

local bus controller, not the external LCLK. LCLK cycle = eLBC controller clock cycle

× LCRR[CLKDIV]. After power on reset,

LBCR[AHD] defaults to 0 and eLBC runs at maximum hold time.

5. System/board must be designed to ensure the input requirement to the device is achieved. Proper device operation is

guaranteed for inputs meeting this requirement by design, simulation, characterization, or functional testing.

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