PIC16F1516 datasheet(189/344 Pages) MICROCHIP

189 / 344 page

 2011 Microchip Technology Inc.

Preliminary

DS41452B-page 189

PIC16(L)F1516/7/8/9

FIGURE 21-4:

SPI MASTER AND MULTIPLE SLAVE CONNECTION

21.2.1

SPI MODE REGISTERS

The MSSP module has five registers for SPI mode

operation. These are:

• MSSP STATUS register (SSPSTAT)

• MSSP Control Register 1 (SSPCON1)

• MSSP Control Register 3 (SSPCON3)

• MSSP Data Buffer register (SSPBUF)

• MSSP Address register (SSPADD)

• MSSP Shift register (SSPSR)

(Not directly accessible)

SSPCON1 and SSPSTAT are the control and STATUS

registers in SPI mode operation. The SSPCON1 regis-

ter is readable and writable. The lower 6 bits of the

SSPSTAT are read-only. The upper two bits of the

SSPSTAT are read/write.

In one SPI master mode, SSPADD can be loaded with

a value used in the Baud Rate Generator. More infor-

mation on the Baud Rate Generator is available in

Section 21.7 “Baud Rate Generator”

SSPSR is the shift register used for shifting data in and

out. SSPBUF provides indirect access to the SSPSR

bytes are written, and from which data bytes are read.

In receive operations, SSPSR and SSPBUF together

create a buffered receiver. When SSPSR receives a

complete byte, it is transferred to SSPBUF and the

SSPIF interrupt is set.

During transmission, the SSPBUF is not buffered. A

write to SSPBUF will write to both SSPBUF and

SSPSR.

SPI Master

SCK

SDO

SDI

General I/O

SCK

SDI

SDO

SPI Slave

SCK

SDI

SDO

SPI Slave

SCK

SDI

SDO

SPI Slave

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