PIC16F1516 datasheet(84/344 Pages) MICROCHIP

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PIC16(L)F1516/7/8/9

DS41452B-page 84

Preliminary

 2011 Microchip Technology Inc.

7.6.5

PIR2 REGISTER

The PIR2 register contains the interrupt flag bits, as

shown in Register 7-5.

Note:

Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the Global

Enable bit, GIE, of the INTCON register.

User

software

should

ensure

the

appropriate interrupt flag bits are clear prior

to enabling an interrupt.

PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2

R/W-0/0

U-0

R/W-0/0

U-0

R/W-0/0

OSFIF

—

—BCLIF

—

CCP2IF

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

x = Bit is unknown

-n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set

‘0’ = Bit is cleared

bit 7

OSFIF:

Oscillator Fail Interrupt Flag bit

= Interrupt is pending

= Interrupt is not pending

bit 6-4

Unimplemented:

Read as ‘0’

bit 3

BCLIF:

MSSP Bus Collision Interrupt Flag bit

= Interrupt is pending

= Interrupt is not pending

bit 2-1

Unimplemented:

Read as ‘0’

bit 0

CCP2IF:

CCP2 Interrupt Flag bit

= Interrupt is pending

= Interrupt is not pending

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