PIC16F1516 datasheet(81/344 Pages) MICROCHIP

81 / 344 page

 2011 Microchip Technology Inc.

Preliminary

DS41452B-page 81

PIC16(L)F1516/7/8/9

7.6.2

PIE1 REGISTER

The PIE1 register contains the interrupt enable bits, as

shown in Register 7-2.

Note:

Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1

R/W-0/0

TMR1GIE

ADIE

RCIE

TXIE

SSPIE

CCP1IE

TMR2IE

TMR1IE

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

x = Bit is unknown

-n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set

‘0’ = Bit is cleared

bit 7

TMR1GIE:

Timer1 Gate Interrupt Enable bit

= Enables the Timer1 Gate Acquisition interrupt

= Disables the Timer1 Gate Acquisition interrupt

bit 6

ADIE:

A/D Converter (ADC) Interrupt Enable bit

= Enables the ADC interrupt

= Disables the ADC interrupt

bit 5

RCIE:

USART Receive Interrupt Enable bit

= Enables the USART receive interrupt

= Disables the USART receive interrupt

bit 4

TXIE:

USART Transmit Interrupt Enable bit

= Enables the USART transmit interrupt

= Disables the USART transmit interrupt

bit 3

SSPIE:

Synchronous Serial Port (MSSP) Interrupt Enable bit

= Enables the MSSP interrupt

= Disables the MSSP interrupt

bit 2

CCP1IE:

CCP1 Interrupt Enable bit

= Enables the CCP1 interrupt

= Disables the CCP1 interrupt

bit 1

TMR2IE:

TMR2 to PR2 Match Interrupt Enable bit

= Enables the Timer2 to PR2 match interrupt

= Disables the Timer2 to PR2 match interrupt

bit 0

TMR1IE:

Timer1 Overflow Interrupt Enable bit

= Enables the Timer1 overflow interrupt

= Disables the Timer1 overflow interrupt

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