BTS6480SF datasheet(28/73 Pages) INFINEON

28 / 73 page

Data Sheet

Rev. 1.0, 2010-04-12

SPOC - BTS6480SF

Automatic PWM Generator

The applied clock signal can be monitored via SPI in the standard diagnosis. The standard diagnosis bit CLE

provides the information in device operation mode (not during stand-by), if the applied clock is above or below the

threshold

PCLK(TH) according to the following table. The bit CLE will be reset after every successful standard

diagnosis readout. The reset of the bit CLE is performed only, if the bit CLE is set.

Note: A changing of the HWCR.CLKTRIM will also change the CLE thresholds.

7.2.2

Internal PWM Clock

The SPOC - BTS6480SF provides also an internal clock signal

INT. The internal clock frequency is used by setting

the register HWCR.CLK to 1

For adjusting the clock signal, a trimming of

INT via the SPI register HWCR.CLK_TRIM can be done. fPWM can be

decreased or increased in steps of

TRIM.

(2)

7.3

PWM Duty Cycle

The PWM duty cycle of each output is defined by the SPI register DCCRn.DC register from 0 to 256. The ON-state

duty cycle is (in %):

(3)

The minimum duty cycle, which can be set (except from 0 %), is according to Equation (3) 0.39 %. The duty cycle

of the output voltage depends on the switching times

ON, tOFF and the connected load. Therefore, the observed

output duty cycle can differ from the set duty cycle.

7.4

Channel Phase Shift

For optimized EMC performances phase shifts between all channels can be programmed via the SPI register

CHCRn.PHS

. The phase shifts refer to one common start point. Please refer to Figure 8. Up to eight different

phase shifts can be selected.

Table 5

External Clock Monitoring

External Clock Status

CLE

Clock Frequency

PCLK > fPCLK(TH)

PCLK < fPCLK(TH)

fPWM

fINT x kTRIM

⋅

()

256 prescaler

⋅

--------------------------------------

DCPWM

DCCRn.DC 100

⋅

256

--------------------------------------------------

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