MSC8152SVT1000B datasheet(61/68 Pages) FREESCALE

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Hardware Design Considerations

MSC8152 Dual-Core Digital Signal Processor Data Sheet, Rev. 1

Freescale Semiconductor

3.5.1.4

DDR2 Unused MAPAR Pin Connections

When the MAPAR signals are not used, refer to Table 43 to determine the correct pin connections.

3.5.2

HSSI-Related Pins

3.5.2.1

HSSI Port Is Not Used

The signal names in Table 44 and Table 45 are generic names for a RapidIO interface. For actual pin names refer to Table 1.

3.5.2.2

HSSI Specific Lane Is Not Used

Table 43. Connectivity of MAPAR Pins for DDR2

Signal Name

Pin connection

MAPAR_OUT

MAPAR_IN

Notes:

For the signals listed in this table, the initial M stands for M1 or M2 depending on which DDR controller is used for DDR2.

For MSC8152 Revision 1 silicon, these pins were connected to GND. For newer revisions of the MSC8152, connecting these

pins to GND increases device power consumption.

Table 44. Connectivity of Serial RapidIO Interface Related Pins When the RapidIO Interface Is Not Used

Signal Name

Pin Connection

SR_IMP_CAL_RX

SR_IMP_CAL_TX

SR[1–2]_REF_CLK

SXCVSS

SR[1–2]_REF_CLK

SXCVSS

SR[1–2]_RXD[3–0]

SXCVSS

SR[1–2]_RXD[3–0]

SXCVSS

SR[1–2]_TXD[3–0]

SR[1–2]_PLL_AVDD

In use

SR[1–2]_PLL_AGND

In use

SXPVSS

In use

SXCVSS

In use

SXPVDD

In use

SXCVDD

In use

Note:

All lanes in the HSSI SerDes should be powered down. Refer to the MSC8152 Reference Manual for details.

Table 45. Connectivity of HSSI Related Pins When Specific Lane Is Not Used

Signal Name

Pin Connection

SR_IMP_CAL_RX

In use

SR_IMP_CAL_TX

In use

SR[1–2]_REF_CLK

In use

SR[1–2]_REF_CLK

In use

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