MSC8152SVT1000B datasheet(41/68 Pages) FREESCALE

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Electrical Characteristics

MSC8152 Dual-Core Digital Signal Processor Data Sheet, Rev. 1

Freescale Semiconductor

Table 22 provides the DDR2 differential specifications for the differential signals MDQS/MDQS and MCK/MCK.

Table 23 provides the DDR3 differential specifications for the differential signals MDQS/MDQS and MCK/MCK.

2.6.2

HSSI AC Timing Specifications

The following subsections define the AC timing requirements for the SerDes reference clocks, the PCI Express data lines, the

Serial RapidIO data lines, and the SGMII data lines.

2.6.2.1

AC Requirements for SerDes Reference Clock

Table 24 lists AC requirements for the SerDes reference clocks.

Note:

Specifications are valid at the recommended operating conditions listed in Table 3.

Table 22. DDR2 SDRAM Differential Electrical Characteristics

Parameter

Symbol

Min

Max

Unit

Input AC differential cross-point voltage

VIXAC

0.5

× GVDD – 0.175

0.5

× GVDD + 0.175

Output AC differential cross-point voltage

VOXAC

0.5

× GVDD – 0.125

0.5

× GVDD + 0.125

Table 23. DDR3 SDRAM Differential Electrical Characteristics

Parameter

Symbol

Min

Max

Unit

Input AC differential cross-point voltage

VIXAC

0.5

× GVDD – 0.150

0.5

× GVDD + 0.150

Output AC differential cross-point voltage

VOXAC

0.5

× GVDD – 0.115

0.5

× GVDD + 0.115

Table 24. SR[1–2]_REF_CLK and SR[1–2]_REF_CLK Input Clock Requirements

Parameter

Symbol

Min

Typical

Max

Units

Notes

SR[1–2]_REF_CLK/SR[1–2]_REF_CLK

frequency range

tCLK_REF

—

100/125

—

MHz

SR[1–2]_REF_CLK/SR[1–2]_REF_CLK clock

frequency tolerance

tCLK_TOL

–350

—

350

ppm

—

SR[1–2]_REF_CLK/SR[1–2]_REF_CLK

reference clock duty cycle (measured at 1.6 V)

tCLK_DUTY

—

SR[1–2]_REF_CLK/SR[1–2]_REF_CLK max

deterministic peak-peak jitter at 10-6 BER

tCLK_DJ

——

—

SR[1–2]_REF_CLK/SR[1–2]_REF_CLK total

reference clock jitter at 10-6 BER (peak-to-peak

jitter at ref_clk input)

tCLK_TJ

——

SR[1–2]_REF_CLK/SR[1–2]_REF_CLK

rising/falling edge rate

tCLKRR/tCLKFR

1—4

V/ns

Differential input high voltage

VIH

200

—

Differential input low voltage

VIL

—

–200

Rising edge rate (SR[1–2]_REF_CLK) to falling

edge rate (SR[1–2]_REF_CLK) matching

Rise-Fall

Matching

——

5, 6

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