MSC8152SVT1000B datasheet(32/68 Pages) FREESCALE

32 / 68 page

MSC8152 Dual-Core Digital Signal Processor Data Sheet, Rev. 1

Electrical Characteristics

Freescale Semiconductor

— For an external AC-coupled connection, there is no common mode voltage requirement for the clock driver.

Because the external AC-coupling capacitor blocks the DC-level, the clock driver and the SerDes reference clock

receiver operate in different command mode voltages. The SerDes reference clock receiver in this connection

scheme has its common mode voltage set to GNDSXC. Each signal wire of the differential inputs is allowed to

swing below and above the command mode voltage GNDSXC. Figure 8 shows the SerDes reference clock input

requirement for AC-coupled connection scheme.

•

Single-Ended Mode

— The reference clock can also be single-ended. The SR[1–2]_REF_CLK input amplitude (single-ended swing)

must be between 400 mV and 800 mV peak-peak (from VMIN to VMAX) with SR[1–2]_REF_CLK either left

unconnected or tied to ground.

— The SR[1–2]_REF_CLK input average voltage must be between 200 and 400 mV. Figure 9 shows the SerDes

reference clock input requirement for single-ended signaling mode.

— To meet the input amplitude requirement, the reference clock inputs may need to be DC- or AC-coupled

externally. For the best noise performance, the reference of the clock could be DC- or AC-coupled into the unused

phase (SR[1–2]_REF_CLK) through the same source impedance as the clock input (SR[1–2]_REF_CLK) in use.

2.5.3.2

DC-Level Requirements for PCI Express Configurations

The DC-level requirements for PCI Express implementations have separate requirements for the Tx and Rx lines. The

MSC8152 supports a 2.5 Gbps PCI Express interface defined by the PCI Express Base Specification, Revision 1.0a. The

transmitter specifications are defined in Table 11 and the receiver specifications are defined in Table 12.

Figure 8. Differential Reference Clock Input DC Requirements (External AC-Coupled)

Figure 9. Single-Ended Reference Clock Input DC Requirements

SR[1–2]_REF_CLK

Vcm

200 mV < Input Amplitude or Differential Peak < 800 mV

Vmax < Vcm + 400 mV

Vmin > Vcm – 400 mV

SR[1–2]_REF_CLK

400 mV < SR[1–2]_REF_CLK Input Amplitude < 800 mV

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