MSC8152SVT1000B datasheet(48/68 Pages) FREESCALE

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MSC8152 Dual-Core Digital Signal Processor Data Sheet, Rev. 1

Electrical Characteristics

Freescale Semiconductor

2.6.5

Ethernet Timing

This section describes the AC electrical characteristics for the Ethernet interface.

There are programmable delay units (PDU) that should be programmed differently for each interface to meet timing. There is

a general configuration register 4 (GCR4) used to configure the timing. For additional information, see the MSC8152 Reference

Manual.

2.6.5.1

Management Interface Timing

Table 33 lists the timer input Ethernet controller management interface timing specifications shown in Table 24.

2.6.5.2

RGMII AC Timing Specifications

Table 34 presents the RGMII AC timing specifications for applications requiring an on-board delayed clock.

Table 33. Ethernet Controller Management Interface Timing

Characteristics

Symbol

Min

Max

Unit

GE_MDC to GE_MDIO delay2

tMDKHDX

GE_MDIO to GE_MDC rising edge setup time

tMDDVKH

7—

GE_MDC rising edge to GE_MDIO hold time

tMDDXKH

0—

Notes:

Program the GE_MDC frequency (fMDC) to a maximum value of 2.5 MHz (400 ns period for tMDC). The value depends on the

source clock and configuration of MIIMCFG[MCS] and UPSMR[MDCP]. For example, for a source clock of 400 MHz to

achieve fMDC = 2.5 MHz, program MIIMCFG[MCS] = 0x4 and UPSMR[MDCP] = 0. See the MSC8152 Reference Manual for

configuration details.

The value depends on the source clock. For example, for a source clock of 267 MHz, the delay is 70 ns. For a source clock of

333 MHz, the delay is 58 ns.

Figure 24. MII Management Interface Timing

Table 34. RGMII at 1 GHz2 with On-Board Delay3 AC Timing Specifications

Parameter/Condition

Symbol

Min

Typ

Max

Unit

Data to clock output skew (at transmitter)4

tSKEWT

–-0.5

—

0.5

Data to clock input skew (at receiver) 4

tSKEWR

1—

2.6

Notes:

At recommended operating conditions with VDDIO of 2.5 V ± 5%.

RGMII at 100 MHz support is guaranteed by design.

Program GCR4 as 0x00000000.

This implies that PC board design requires clocks to be routed such that an additional trace delay of greater than 1.5 ns and

less than 2.0 ns is added to the associated clock signal.

GE_MDC

GE_MDIO

(Input)

(Output)

tMDC

tMDDXKH

tMDDVKH

tMDKHDX

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