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MSC8152SVT1000B bảng dữ liệu(PDF) 51 Page - Freescale Semiconductor, Inc |
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MSC8152SVT1000B bảng dữ liệu(HTML) 51 Page - Freescale Semiconductor, Inc |
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51 / 68 page ![]() MSC8152 Dual-Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor 51 2.6.7 Asynchronous Signal Timing Table 35 lists the asynchronous signal timing specifications. The following interfaces use the specified asynchronous signals: • GPIO. Signals GPIO[31–0], when used as GPIO signals, that is, when the alternate multiplexed special functions are not selected. Note: When used as a general purpose input (GPI), the input signal should be driven until it is acknowledged by the MSC8152 device, that is, when the expected input value is read from the GPIO data register. • EE port. Signals EE0, EE1. • Boot function. Signal STOP_BS. • I 2C interface. Signals I2C_SCL and I2C_SDA. • Interrupt inputs. Signals IRQ[15–0] and NMI. • Interrupt outputs. Signals INT_OUT and NMI_OUT (minimum pulse width is 32 ns). 2.6.8 JTAG Signals Table 38 lists the JTAG timing specifications shown in Figure 29 through Figure 32. Figure 29 shows the test clock input timing diagram Table 37. Signal Timing Characteristics Symbol Type Min Input tIN Asynchronous One CLKIN cycle Output tOUT Asynchronous Application dependent Note: Input value relevant for EE0, IRQ[15–0], and NMI only. Table 38. JTAG Timing Characteristics Symbol All frequencies Unit Min Max TCK cycle time tTCKX 36.0 — ns TCK clock high phase measured at VM = VDDIO/2 tTCKH 15.0 — ns Boundary scan input data setup time tBSVKH 0.0 — ns Boundary scan input data hold time tBSXKH 15.0 — ns TCK fall to output data valid tTCKHOV — 20.0 ns TCK fall to output high impedance tTCKHOZ — 24.0 ns TMS, TDI data setup time tTDIVKH 0.0 — ns TMS, TDI data hold time tTDIXKH 5.0 — ns TCK fall to TDO data valid tTDOHOV — 10.0 ns TCK fall to TDO high impedance tTDOHOZ — 12.0 ns TRST assert time tTRST 100.0 — ns Note: All timings apply to OnCE module data transfers as well as any other transfers via the JTAG port. Figure 29. Test Clock Input Timing TCK (Input) VM VM tTCKX tTCKH tTCKR tTCKR |
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