MAXQ3181-RAN+ datasheet(56/84 Pages) MAXIM

56 / 84 page

Low-Power, Active Energy, Polyphase AFE

______________________________________________________________________________________

OV: The RMS voltage on one or more of the phases

over the most recent DSP cycle has exceeded the

value set in the OVLVL register.

UV: The RMS voltage on one or more of the phases

over the most recent DSP cycle has failed to exceed

the value set in the UVLVL register.

NOZX: Zero crossings were not detected on one or

more of the phases. The detection time is defined in

the NZX_TIMO register. The resolution for the

NZX_TIMO register is the duration of one ADC sam-

ple time (nominally 40μs).

DCHA: Tells the host processor that the direction of

net real energy flow on one of the three phases has

changed during the current DSP cycle as compared

to the previous DSP cycle.

DSPRDY: Indicates the latest DSP cycle has just

completed.

DSPOR: Indicates that the processing for the previ-

ous DSP cycle had not been completed before the

current DSP cycle became available for processing.

This overflow indication should never be seen in the

default configuration; however, under some condi-

tions (faster ADC rate, slower CPU clock) the pro-

cessing requirements may exceed the number of

CPU cycles available for DSP processing. Under

these circumstances, the clock rate may be

increased, the ADC rate may be reduced (that is,

the R_ADCRATE register may be increased).

Note that when DSPOR becomes set, all DSP calcu-

lations as well as the pulse output are invalidated.

The appropriate host response is to take the remedi-

al action described above and discard the current

set of DSP result values.

Each phase has a local register that contains copies of

the OC, OV, UV, NOZX, and DCHA bits. Thus, to deter-

mine which phase(s) have exception conditions

requires four reads: the IRQ_FLAG register to deter-

mine which conditions are active that are causing the

interrupt to occur, and then a read to A.FLAGS,

B.FLAGS, and C.FLAGS to determine which of the

phases have the indicated condition.

Finally, each phase has a pair of local registers that

contain overflow flags for each energy accumulator. If

the EOVF bit is set in the IRQ_FLAG register, the host

should then read the A.EOVER, B.EOVER, and

C.EOVER registers to determine which of the phases

have overflow conditions.

Overvoltage and Overcurrent Detection

The MAXQ3181 detects overvoltage and overcurrent

events and can issue interrupt request signals to the

master when these events occur. The overvoltage level

can be programmed into the OVLVL register, while the

overcurrent level is determined by the OCLVL register.

Both OVLVL and OCLVL registers represent the bits

23:8 of the VRMS or IRMS registers. Any time the

MAXQ3181 detects the RMS-value exceeding a thresh-

old level, the OV or OC interrupt flag is set. If enabled,

any of these flags issues an interrupt request. All inter-

rupt flags are “sticky” bits—the MAXQ3181 never

clears them on its own unless a reset occurs. The inter-

rupt flags should be cleared by the master by writing

the appropriate register.

Meter Units to Real Units Conversion

All energy calculations, including various threshold

checks, are performed internally in fixed format in meter

units. Therefore, the threshold values must be supplied

by the user in meter units as well. This section summa-

rizes how to convert real units (V, A, kWh, W, and kAh)

into meter units and vice versa.

The conversion factors are based on the settings of tFR,

VFS, and IFS, defined by the user’s design.

tFR is analog scan frame timing. This parameter is

defined by the R_ADCRATE setting and system clock

frequency fSYS:

tFR = (R_ADCRATE + 1) x 8/fSYS

Default conditions are R_ADCRATE = 319, fSYS = 8MHz.

VFS is full-scale voltage. This is the input voltage that

produces full-scale ADC output; defined by the hard-

ware voltage transducer ratio VTR and ADC full-scale

input voltage VFSADC:

VFS = VFSADC x VTR

Default conditions are VFSADC = 1.024V. VTR is design

dependent.

IFS is full-scale current. This is the input current that

produces full-scale ADC output; defined by the hard-

ware current transducer ratio ITR and ADC full-scale

input voltage VFSADC:

IFS = VFSADC x ITR

Default conditions are VFSADC = 1.024V. ITR is design

dependent.

Meter units are defined with respect to the base para-

meters as shown in Table 5.

MAXQ3181-RAN+ bảng dữ liệu(PDF) 56 Page - Maxim Integrated Products

MAXQ3181-RAN+ bảng dữ liệu(HTML) 56 Page - Maxim Integrated Products

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84

bảng dữ liệu tải về

Link URL