MAXQ3181-RAN+ datasheet(32/84 Pages) MAXIM

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Low-Power, Active Energy, Polyphase AFE

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Interrupt Mask Register (IRQ_MASK) (0x006)

BIT

NAME

FUNCTION

EDSPOR

When set, the DSPOR flag causes the IRQ pin to become active.

EDSPRDY

When set, this flag causes the IRQ pin to become active.

13, 7:3

—

Reserved.

EDCHA

When set, this flag causes the IRQ pin to become active when the direction of real energy flow has

been observed to have changed (that is, from toward the load to away from the load, or from away from

the load to toward the load).

ENOZX

When set, this flag causes the IRQ pin to become active when the MAXQ3181 has failed to detect zero

crossings on one or more voltage channels for at least one DSP cycle.

EUV

When set, this flag causes the IRQ pin to become active when the absolute instantaneous voltage

level in one or more voltage channels failed to exceed the trip level set in the UVLVL (Undervoltage

Level) register for one DSP cycle.

EOV

When set, this flag causes the IRQ pin to become active when the absolute instantaneous voltage

level in one or more voltage channels has exceeded the trip level set in the OVLVL (Overvoltage Level)

EOC

When set, this flag causes the IRQ pin to become active when absolute instantaneous current in one

or more current channels has exceeded the trip level set in the OCLVL (Overcurrent Level) register.

EEOVF

When set, this flag causes the IRQ pin to become active when one or more energy accumulators have

an overflow condition from their MSB.

ECHSCH

When set, this flag enables the IRQ pin to become active when a CHKSUM change is detected.

EPWRF

When set, this flag causes the IRQ pin to become active when a power-supply failure is imminent and

the supervisory processor should begin taking steps to save its state and prepare for a loss of power.

Bit:

Name:

EDSPOR

EDSPRDY

—

EDCHA

ENOZX

EUV

EOV

EOC

Reset:

Bit:

Name:

—

EEOVF

ECHSCH

EPWRF

Reset:

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