MAXQ3181-RAN+ datasheet(26/84 Pages) MAXIM

26 / 84 page

Low-Power, Active Energy, Polyphase AFE

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RAM-Based Registers

The RAM-based registers contain both operating parameters and measurement results. They are divided into a num-

ber of categories that are described in the following sections.

General Operating Registers

Global Status Register (STATUS) (0x000)

This register contains bits that reflect the global status of the device.

Bit:

Name:

—

CROFF

PORF

WDTR

—

PHSEQ

—

REVCFP

Reset:

BIT

NAME

FUNCTION

7, 3, 1

—

Reserved.

CROFF

When set, the high-frequency crystal has failed and the MAXQ3181 is operating from its internal ring

oscillator. Under these circumstances, energy accumulation is not accurate and the SPI bus does not

operate at full speed.

PORF

When set, the last reset was due to power-on-reset. Host should clear this bit to allow the next POR

detection.

WDTR

When set, the last reset was caused by expired watchdog. The bit should be cleared (set to 0) by the

host to allow the next watchdog reset detection.

PHSEQ

0 = The sequence of voltages presented to the voltage inputs is (-A-B-C-).

1 = The sequence of voltages presented to the voltage inputs is reversed (-A-C-B-).

This bit is meaningful only for connection systems that include all three voltages.

REVCFP

0 = The quantity being output on the CFP pin is positive (direct).

1 = The quantity being output on the CFP pin is negative (reverse).

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