MPC8610EC datasheet(13/96 Pages) FREESCALE

13 / 96 page

Pin Assignments and Reset States

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 0

Freescale Semiconductor

SGND

A5, A8, A13, A17, A21, B15, B19, C4, C9,

C12, C16, C20, C22, D6, D9, D10, D11,

D14, D18, D22, E5, E6, E7, E8, E9, E10,

E13, E14, E15, E16, E17, E18, E19, E20

Ground pins for

SVDD

XGND

E12, F9, F15, F19, F23, G13, G17, G21,

H10, H16, H20, J8, J12, J14, J18, K8, K9,

K11, K15, K17, K19, K21

Ground pins for

XVDD

Reset Configuration Signals15

LAD[0:31]

cfg_gpinout[0:31]

AA21, AA22, AA23, Y21, Y22, Y23, Y24,

W23, W24, W25, V28, V27, V25, V23, V21,

W22, U28, U26, U24, U22, U23, U20, U21,

W20, V20, T24, T25, T27, T26, T21, T22,

T23

—BVDD

LA10/SSI1_TXD

cfg_ssi_la_sel

P19

—

BVDD

LA[25:26]

cfg_elbc_clkdiv[0:1]

M23, N23

—

BVDD

LA27

cfg_cpu_boot

N24

—

BVDD

DIU_LD[10], LA[28:31]

cfg_sys_pll[0:4]

R6, M26, N20, N21, N22

—

BVDD

LWE0/LFWE/LBS0

cfg_pci_speed

T19

—

BVDD

LWE/LBS[1:3]

cfg_host_agt[0:2]

T20, W19, T18

—

BVDD

LBCTL, LALE,

LGPL2/LOE/LFRE,

DIU_LD4

cfg_core_pll[0:3]

T28, R28, L21, W4

—

BVDD

LGPL0/LFCLE

cfg_net2_div

L19

—

BVDD

LGPL1/LFALE

cfg_pci_clk

L20

—

BVDD

LGPL3/LFWP, LGPL5

cfg_boot_seq[0:1]

L22, L24

—

BVDD

DIU_LD[0]

cfg_elbc_ecc

—

OVDD

DIU_LD[7:9]

cfg_io_ports[0:2]

U5, T7, R4

—

OVDD

DIU_LD[11:12]

cfg_dram_type[0:1]

R7, R8

—

OVDD

Table 1. Signal Reference by Functional Block (continued)

Name1

Package Pin Number

Pin Type

Power Supply

Notes

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