MPC8610EC datasheet(26/96 Pages) FREESCALE

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MPC8610 Integrated Host Processor Hardware Specifications, Rev. 0

Electrical Characteristics

Freescale Semiconductor

2.4.5

Other Input Clocks

For information on the input clocks of other functional blocks of the platform such as SerDes see the specific section of this

document.

2.5

RESET Initialization

Table 12 describes the AC electrical specifications for the RESET initialization timing requirements of the MPC8610.

Table 13 provides the PLL lock times.

2.6

DDR and DDR2 SDRAM

This section describes the DC and AC electrical specifications for the DDR SDRAM interface of the MPC8610. Note that DDR

SDRAM is GVDD = 2.5 V and DDR2 SDRAM is GVDD = 1.8 V.

Table 12. RESET Initialization Timing Specifications

Parameter/Condition

Min

Max

Unit

Notes

Required assertion time of HRESET

100

—

μs

Minimum assertion time for SRESET

—

SYSCLKs

Platform PLL input setup time with stable SYSCLK before HRESET

negation

100

—

μs2

Input setup time for POR configs (other than PLL config) with respect to

negation of HRESET

—

SYSCLKs

Input hold time for all POR configs (including PLL config) with respect to

negation of HRESET

—

SYSCLKs

Maximum valid-to-high impedance time for actively driven POR configs

with respect to negation of HRESET

—

SYSCLKs

Notes:

1. SYSCLK is he primary clock input for the device.

2. This is related to HRESET assertion time.

Table 13. PLL Lock Times

Parameter/Condition

Min

Max

Unit

Notes

PLL lock times (platform, PCI and e600 core)

—

100

μs1

Notes:

1. The PLL lock time for the e600 core PLL requires an additional 255 platform clock cycles.

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