MPC8610EC datasheet(58/96 Pages) FREESCALE

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MPC8610 Integrated Host Processor Hardware Specifications, Rev. 0

Electrical Characteristics

Freescale Semiconductor

Figure 33. Single-Ended Reference Clock Input DC Requirements

2.17.2.3

Interfacing With Other Differential Signaling Levels

•

With on-chip termination to SGND, the differential reference clocks inputs are HCSL (high-speed current steering

logic) compatible DC-coupled.

•

Many other low voltage differential type outputs like LVDS (low voltage differential signaling) can be used but may

need to be AC-coupled due to the limited common mode input range allowed (100 to 400 mV) for DC-coupled

connection.

•

LVPECL outputs can produce signal with too large amplitude and may need to be DC-biased at clock driver output

first, then followed with series attenuation resistor to reduce the amplitude, in addition to AC-coupling.

NOTE

Figure 34 to Figure 37 are for conceptual reference only. Due to the fact that clock driver

chip's internal structure, output impedance and termination requirements are different

between various clock driver chip manufacturers, it is very possible that the clock circuit

reference designs provided by clock driver chip vendor are different from what is shown

below. They might also vary from one vendor to the other. Therefore, Freescale

Semiconductor can neither provide the optimal clock driver reference circuits nor

guarantee the correctness of the following clock driver connection reference circuits. The

system designer is recommended to contact the selected clock driver chip vendor for the

optimal reference circuits with the MPC8610 SerDes reference clock receiver requirement

provided in this document.

Figure 34 shows the SerDes reference clock connection reference circuits for HCSL type clock driver. It assumes that the DC

levels of the clock driver chip is compatible with MPC8610 SerDes reference clock input’s DC requirement.

n_REF_CLK

400 mV < SD

n_REF_CLK Input Amplitude < 800 mV

0 V

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