MPC8610EC datasheet(72/96 Pages) FREESCALE

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MPC8610 Integrated Host Processor Hardware Specifications, Rev. 0

Hardware Design Considerations

Freescale Semiconductor

Figure 47 provides the boundary-scan timing diagram.

Figure 47. Boundary-Scan Timing Diagram

Hardware Design Considerations

This section provides electrical and thermal design recommendations for successful application of the MPC8610.

3.1

System Clocking

This section describes the PLL configuration of the MPC8610. Note that the platform clock is identical to the internal MPX bus

clock.

This device includes six PLLs, as follows:

The platform PLL generates the platform clock from the externally supplied SYSCLK input. The frequency ratio

between the platform and SYSCLK is selected using the platform PLL ratio configuration bits as described in

Section 3.1.2, “Platform/MPX to SYSCLK PLL Ratio.”

The e600 core PLL generates the core clock from the platform clock. The frequency ratio between the e600 core

clock and the platform clock is selected using the e600 PLL ratio configuration bits as described in Section 3.1.3,

“e600 Core to MPX/Platform Clock PLL Ratio.”

The PCI PLL generates the clocking for the PCI bus

Each of the two SerDes blocks has a PLL.

VM = Midpoint Voltage (OVDD/2)

tJTDVKH

tJTDXKH

Boundary

Data Outputs

Boundary

Data Outputs

JTAG

External Clock

Boundary

Data Inputs

Output Data Valid

tJTKLDX

tJTKLDZ

tJTKLDV

Input

Data Valid

Output Data Valid

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